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1. 发明授权

US11983131B2 Network and edge acceleration tile (NEXT) architecture 有权
公开(公告)号：US11983131B2
公开(公告)日：2024-05-14
申请号：US17134361
申请日：2020-12-26
申请人： Intel Corporation
发明人： Patrick G. Kutch , Andrey Chilikin , Niall D. McDonnell , Brian A. Keating , Naveen Lakkakula , Ilango S. Ganga , Venkidesh Krishna Iyer , Patrick Fleming , Lokpraveen Mosur
IPC分类号： G06F13/40 , G06F3/06 , G06F9/50 , G06F12/0802 , G06F13/42
CPC分类号： G06F13/4027 , G06F3/0604 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F9/5083 , G06F12/0802 , G06F13/4221 , G06F2212/6042 , G06F2213/0026 , G06F2213/40
摘要： Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

2. 发明申请

US20190205139A1 SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS 审中-公开
公开(公告)号：US20190205139A1
公开(公告)日：2019-07-04
申请号：US15858899
申请日：2017-12-29
申请人： Intel Corporation
发明人： Christopher J. Hughes , Joseph Nuzman , Jonas Svennebring , Doddaballapur N. Jayasimha , Samantika S. Sury , David A. Koufaty , Niall D. McDonnell , Yen-Cheng Liu , Stephen R. Van Doren , Stephen J. Robinson
IPC分类号： G06F9/30
摘要： Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

3. 发明授权

US11489791B2 Virtual switch scaling for networking applications 有权
公开(公告)号：US11489791B2
公开(公告)日：2022-11-01
申请号：US16177262
申请日：2018-10-31
申请人： Intel Corporation
发明人： Niall D. McDonnell , Bruce Richardson , John Mangan , Harry Van Haaren , Ciara Loftus , Brian A. Keating
IPC分类号： G06F13/10 , H04L49/00 , G06F9/54 , H04L49/9005
摘要： Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

4. 发明申请

US20210385720A1 SOFTWARE-DEFINED NETWORKING DATA RE-DIRECTION 有权
公开(公告)号：US20210385720A1
公开(公告)日：2021-12-09
申请号：US17184832
申请日：2021-02-25
申请人： Intel Corporation
发明人： Jonas Svennebring , Niall D. McDonnell , Andrey Chilikin , Andrew Cunningham , Christopher MacNamara , Carl-Oscar Montelius , Eliezer Tamir , Bjorn Topel
IPC分类号： H04W36/30 , H04W36/32 , H04L12/715 , H04W76/27 , H04L12/717 , H04W40/18
摘要： Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

5. 发明申请

US20200285578A1 SOFTWARE-TRANSPARENT HARDWARE PREDICTOR FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION 审中-公开
公开(公告)号：US20200285578A1
公开(公告)日：2020-09-10
申请号：US16822939
申请日：2020-03-18
申请人： Intel Corporation
发明人： Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
IPC分类号： G06F12/0831 , G06F12/084 , G06F12/0811
摘要： Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

6. 发明授权

US10445271B2 Multi-core communication acceleration using hardware queue device 有权
公开(公告)号：US10445271B2
公开(公告)日：2019-10-15
申请号：US14987676
申请日：2016-01-04
申请人： Intel Corporation
发明人： Ren Wang , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Yipeng Wang , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson
IPC分类号： G06F13/37 , G06F12/0811 , G06F13/16 , G06F12/0868 , G06F12/04 , G06F9/38
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

7. 发明申请

US20190007318A1 TECHNOLOGIES FOR INFLIGHT PACKET COUNT LIMITING IN A QUEUE MANAGER ENVIRONMENT 审中-公开
公开(公告)号：US20190007318A1
公开(公告)日：2019-01-03
申请号：US15638728
申请日：2017-06-30
申请人： Intel Corporation
发明人： Niall D. McDonnell , William Burroughs , Nitin N. Garegrat , David P. Sonnier
IPC分类号： H04L12/803 , H04L12/859 , H04L12/801 , H04L12/805 , H04L12/863
摘要： Technologies for inflight packet count limiting include a network device. The network device is to receive a packet from a producer application. The packet is configured to be enqueued into a packet queue as a queue element to be consumed by a consumer application. The network device is also to increment, in response to receipt of the packet, an inflight count variable, determine whether a value of the inflight count variable satisfies an inflight count limit, and enqueue, in response to a determination that the value of the inflight count variable satisfies the inflight count limit, the packet.

8. 发明授权

US09553853B2 Techniques for load balancing in a packet distribution system 有权
标题翻译：分组分发系统中的负载均衡技术
公开(公告)号：US09553853B2
公开(公告)日：2017-01-24
申请号：US14582098
申请日：2014-12-23
申请人： Intel Corporation
发明人： Tomasz Kantecki , Niall D. McDonnell
IPC分类号： H04L29/06
CPC分类号： H04L63/0442
摘要： Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及以负载平衡方式在多个核之间分配加密分组以进行进一步处理的技术。设备可以包括处理器组件; 解密组件，用于解密加密分组以从加密分组生成解密分组，所述加密分组包括包含至少一个信息字段的报头; 散列组件，用于在由所述解密组件解密所述加密分组的至少一部分期间从所述至少一个信息字段生成标题散列，所述标题散列包括比所述至少一个信息字段少的位数; 以及分发组件，用于基于所述头部散列来选择耦合到所述处理器组件的多个核心的第一核心，并且从所述处理器组件向所述第一核心传送所述解密的分组。描述和要求保护其他实施例。

9. 发明授权

US12135981B2 Systems, methods, and apparatuses for heterogeneous computing 有权
公开(公告)号：US12135981B2
公开(公告)日：2024-11-05
申请号：US18207870
申请日：2023-06-09
申请人： Intel Corporation
发明人： Rajesh M. Sankaran , Gilbert Neiger , Narayan Ranganathan , Stephen R. Van Doren , Joseph Nuzman , Niall D. McDonnell , Michael A. O'Hanlon , Lokpraveen B. Mosur , Tracy Garrett Drysdale , Eriko Nurvitadhi , Asit K. Mishra , Ganesh Venkatesh , Deborah T. Marr , Nicholas P. Carter , Jonathan D. Pearce , Edward T. Grochowski , Richard J. Greco , Robert Valentine , Jesus Corbal , Thomas D. Fletcher , Dennis R. Bradford , Dwight P. Manley , Mark J. Charney , Jeffrey J. Cook , Paul Caprioli , Koichi Yamada , Kent D. Glossop , David B. Sheffield
IPC分类号： G06F9/48 , G06F9/30 , G06F9/38
CPC分类号： G06F9/48 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/383
摘要： Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

10. 发明公开

US20230185732A1 TRANSPARENT ENCRYPTION 审中-公开
公开(公告)号：US20230185732A1
公开(公告)日：2023-06-15
申请号：US18107399
申请日：2023-02-08
申请人： Intel Corporation
发明人： Weigang Li , Changzheng Wei , John Barry , Maryam Tahhan , Jonas Alexander Svennebring , Niall D. McDonnell , Alexander Leckey , Patrick Fleming , Christopher MacNamara , John Joseph Browne
IPC分类号： G06F12/14 , G06F13/16 , G06F13/28 , G06F21/53 , G06F21/60 , G06F21/79
CPC分类号： G06F12/1408 , G06F13/1668 , G06F13/28 , G06F21/53 , G06F21/602 , G06F21/606 , G06F21/79 , G06F2213/0038
摘要： There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

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