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1. 发明公开

US20230176987A1 MANY-TO-MANY PCIE SWITCH 审中-公开
公开(公告)号：US20230176987A1
公开(公告)日：2023-06-08
申请号：US18082485
申请日：2022-12-15
申请人： Intel Corporation
发明人： Patrick Connor , Matthew A. JARED , Duke C. HONG , Elizabeth M. KAPPLER , Chris Pavlas , Scott P. Dubal
IPC分类号： G06F13/40
CPC分类号： G06F13/4022
摘要： Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

2. 发明授权

US11593292B2 Many-to-many PCIe switch 有权
公开(公告)号：US11593292B2
公开(公告)日：2023-02-28
申请号：US16894437
申请日：2020-06-05
申请人： INTEL CORPORATION
发明人： Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
IPC分类号： G06F13/00 , G06F13/40
摘要： Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

3. 发明申请

US20220191602A1 OUT-OF-BAND PLATFORM TUNING AND CONFIGURATION 有权
公开(公告)号：US20220191602A1
公开(公告)日：2022-06-16
申请号：US17687132
申请日：2022-03-04
申请人： Intel Corporation
发明人： Andrew J. Herdrich , Patrick L. Connor , Dinesh Kumar , Alexander W. MIN , Daniel J. DAHLE , Kapil Sood , Jeffrey B. SHAW , Edwin Verplanke , Scott P. Dubal , James Robert Hearn
IPC分类号： H04Q9/02 , H04L41/5019 , H04L41/5009 , H04L43/10
摘要： Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.

4. 发明申请

US20210318885A1 ACCELERATING NETWORK SECURITY MONITORING 有权
公开(公告)号：US20210318885A1
公开(公告)日：2021-10-14
申请号：US17213132
申请日：2021-03-25
申请人： Intel Corporation
发明人： Kapil Sood , Andrew J. Herdrich , Scott P. Dubal , Patrick L. Connor , James Robert Hearn , Niall D. McDonnell
IPC分类号： G06F9/38 , H04L29/06
摘要： Generally discussed herein are systems, devices, and methods for network security monitoring (NSM). A hardware queue manager (HQM) may include an input interface to receive first data from at least a first worker thread, queue duplication circuitry to generate a copy of at least a portion of the first data to create first copied data, and an output interface to (a) provide the first copied data to a second worker thread, and/or (b) provide at least a portion of the first data to a third worker thread.

5. 发明申请

US20210041929A1 DYNAMIC NETWORK CONTROLLER POWER MANAGEMENT 有权
公开(公告)号：US20210041929A1
公开(公告)日：2021-02-11
申请号：US17076776
申请日：2020-10-21
申请人： Intel Corporation
发明人： Patrick Lewis Connor , James R. Hearn , Kevin D. Liedtke , Scott P. Dubal , Benjamin Cheong , Rafael Guerra
IPC分类号： G06F1/26 , G06F13/20
摘要： An I/O controller includes a port to couple to a network, a buffer to buffer network data, and an interface to support a link to couple the I/O controller to another device. The I/O controller monitors a buffer to determine an amount of traffic on the port, initiates, at the interface, a power management transition on the link based on the amount of traffic, and mitigate latency associated with the power management transition at the port.

6. 发明申请

US20180181421A1 TRANSFERRING PACKETS BETWEEN VIRTUAL MACHINES VIA A DIRECT MEMORY ACCESS DEVICE 审中-公开
公开(公告)号：US20180181421A1
公开(公告)日：2018-06-28
申请号：US15391777
申请日：2016-12-27
申请人： Intel Corporation
发明人： Patrick Connor , Scott P. Dubal , James R. Hearn , Iosif Gasparakis , Chris Pavlas , Eliezer Tamir
IPC分类号： G06F9/455 , G06F9/50
CPC分类号： G06F9/45558 , G06F9/54 , G06F15/17306 , G06F2009/45583
摘要： An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.

7. 发明授权

US09942631B2 Out-of-band platform tuning and configuration 有权
公开(公告)号：US09942631B2
公开(公告)日：2018-04-10
申请号：US14866567
申请日：2015-09-25
申请人： Intel Corporation
发明人： Andrew J Herdrich , Patrick L. Connor , Dinesh Kumar , Alexander W Min , Daniel J. Dahle , Kapil Sood , Jeffrey B Shaw , Edwin Verplanke , Scott P. Dubal , James Robert Hearn
IPC分类号： H04Q9/02 , H04L12/26 , H04L12/24
CPC分类号： H04Q9/02 , H04L41/5009 , H04L41/5019 , H04L43/08 , H04L43/10
摘要： Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.

8. 发明申请

US20170250892A1 TECHNOLOGIES FOR INDEPENDENT SERVICE LEVEL AGREEMENT MONITORING 审中-公开
公开(公告)号：US20170250892A1
公开(公告)日：2017-08-31
申请号：US15056570
申请日：2016-02-29
申请人： Intel Corporation
发明人： Trevor Cooper , Kapil Sood , Scott P. Dubal , Michael Hingston McLaughlin Bursell , Jesse C. Brandeburg , Stephen T. Palermo
IPC分类号： H04L12/26 , G06F21/44
CPC分类号： G06F21/44 , G06F21/552 , H04L41/5009 , H04L41/5019
摘要： Technologies for monitoring service level agreement (SLA) performance in an end-to-end SLA monitoring architecture include a network functions virtualization (NFV) SLA controller configured to manage SLA agents initialized in various network processing components of the end-to-end SLA monitoring architecture. To do so, the NFV SLA controller is configured to provide instruction to the SLA agents indicating which types of telemetry data to monitor and receive the requested telemetry data, as securely collected and securely packaged by the SLA agents. The NFV SLA controller is further configured to securely analyze the received telemetry data to determine one or more performance metrics and compare performance benchmarks against the performance metrics to generate an SLA report that includes the results of the comparison. Other embodiments are described and claimed.

9. 发明授权

US11960429B2 Many-to-many PCIE switch 有权
公开(公告)号：US11960429B2
公开(公告)日：2024-04-16
申请号：US18082485
申请日：2022-12-15
申请人： Intel Corporation
发明人： Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
IPC分类号： G06F13/00 , G06F13/40
CPC分类号： G06F13/4022
摘要： Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

10. 发明授权

US10178054B2 Method and apparatus for accelerating VM-to-VM network traffic using CPU cache 有权
公开(公告)号：US10178054B2
公开(公告)日：2019-01-08
申请号：US15088910
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： Stephen T. Palermo , Iosif Gasparakis , Scott P. Dubal , Kapil Sood , Trevor Cooper , Jr-Shian Tsai , Jesse C. Brandeburg , Andrew J. Herdrich , Edwin Verplanke
IPC分类号： H04L12/861 , H04L12/715 , H04L12/931 , G06F15/173
摘要： Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

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