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1. 发明申请

WO2016060859A1 AN INTERFACE BETWEEN A DEVICE AND A SECURE PROCESSING ENVIRONMENT 审中-公开
标题翻译：设备之间的界面和安全的处理环境
公开(公告)号：WO2016060859A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/053526
申请日：2015-10-01
申请人： INTEL CORPORATION
发明人： NARENDRA TRIVEDI, Alpa , CHHABRA, Siddhartha , KANG, Xiaozhu , DEWAN, Prashant , SAVAGAONKAR, Uday , DURHAM, David
IPC分类号： G06F21/53
CPC分类号： G06F21/53 , G06F2221/033
摘要： Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
摘要翻译：公开了用于设备和安全处理环境之间的接口的发明的实施例。在一个实施例中，系统包括处理器，设备和接口插件。处理器包括指令单元和执行单元。指令单元将接收创建安全处理环境的指令。执行单元在安全处理环境中执行应用。该设备将为应用程序执行工作负载。接口插件是为设备提供一个接口，进入安全处理环境以执行工作负载。

2. 发明申请

WO2014098998A1 SECURING DATA TRANSMISSIONS BETWEEN PROCESSOR PACKAGES 审中-公开
标题翻译：保护处理器包之间的数据传输
公开(公告)号：WO2014098998A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/047279
申请日：2013-06-24
申请人： INTEL CORPORATION , JOHNSON, Simon , DAS, Abhishek , ROZAS, Carlos , SAVAGAONKAR, Uday , BLANKENSHIP, Robert , PADWEKAR, Kiran
发明人： JOHNSON, Simon , DAS, Abhishek , ROZAS, Carlos , SAVAGAONKAR, Uday , BLANKENSHIP, Robert , PADWEKAR, Kiran
IPC分类号： G06F21/60
CPC分类号： H04L9/00 , G06F21/556 , G06F21/606 , H04L9/32 , H04L63/0428 , H04L63/0471 , H04L63/123
摘要： Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.
摘要翻译：公开了用于确保处理器封装之间的传输的发明的实施例。在一个实施例中，一种装置包括加密单元，用于直接通过点对点链路加密要从装置发送到处理器包的第一内容。

3. 发明申请

WO2010057065A2 METHOD AND APPARATUS TO PROVIDE SECURE APPLICATION EXECUTION 审中-公开
标题翻译：提供安全应用执行的方法和设备
公开(公告)号：WO2010057065A2
公开(公告)日：2010-05-20
申请号：PCT/US2009/064493
申请日：2009-11-14
申请人： INTEL CORPORATION , MCKEEN, Frank , SAVAGAONKAR, Uday , ROZAS, Carlos, V. , GOLDSMITH, Michael, A. , HERBERT, Howard, C. , ALTMAN, Asher , GRAUNKE, Gary , DURHAM, David , JOHNSON, Simon, P. , KOUNAVIS, Michael, E. , SCARLATA, Vincent, R. , CIHULA, Joseph , JEYASINGH, Stalinselvaraj , LINT, Bernard , NEIGER, Gil , RODGERS, Dion , BRICKELL, Ernie , LI, Jianguo
发明人： MCKEEN, Frank , SAVAGAONKAR, Uday , ROZAS, Carlos, V. , GOLDSMITH, Michael, A. , HERBERT, Howard, C. , ALTMAN, Asher , GRAUNKE, Gary , DURHAM, David , JOHNSON, Simon, P. , KOUNAVIS, Michael, E. , SCARLATA, Vincent, R. , CIHULA, Joseph , JEYASINGH, Stalinselvaraj , LINT, Bernard , NEIGER, Gil , RODGERS, Dion , BRICKELL, Ernie , LI, Jianguo
IPC分类号： G06F21/24 , G06F9/06 , G06F3/06 , G06F9/44
CPC分类号： G06F9/30043 , G06F9/30032 , G06F21/56
摘要： A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
摘要翻译：一种在计算机系统内实现安全应用和数据完整性的技术。在一个实施例中，建立一个或多个安全空间，其中可以存储和执行应用和数据。

4. 发明申请

WO2015148834A1 VIRTUALIZATION BASED INTRA-BLOCK WORKLOAD ISOLATION 审中-公开
标题翻译：基于虚拟化的内部工作负载隔离
公开(公告)号：WO2015148834A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022802
申请日：2015-03-26
申请人： INTEL CORPORATION
发明人： PRASHANT, Dewan , SENGUPTA, Uttam , CHHABRA, Siddhartha , DURHAM, David , KANG, Xiaozhu , SAVAGAONKAR, Uday , NARENDRA TRIVEDI, Alpha
IPC分类号： G06F21/53 , G06F9/455
CPC分类号： G06F21/53 , G06F9/45558 , G06F21/84 , G06F2009/45587 , G06F2213/0038 , H04L9/3247
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for virtualization-based intra-block workload isolation. The system may include a virtual machine manager (VMM) module to create a secure virtualization environment or sandbox. The system may also include a processor block to load data into a first region of the sandbox and to generate a workload package based on the data. The workload package is stored in a second region of the sandbox. The system may further include an operational block to fetch and execute instructions from the workload package.
摘要翻译：通常，本公开提供了用于基于虚拟化的块内工作负载隔离的系统，设备，方法和计算机可读介质。该系统可以包括用于创建安全虚拟化环境或沙箱的虚拟机管理器（VMM）模块。该系统还可以包括处理器块，用于将数据加载到沙箱的第一区域中，并且基于该数据生成工作负载包。工作负载包存储在沙箱的第二个区域。系统还可以包括用于从工作负载包获取和执行指令的操作块。

5. 发明申请

WO2014004151A2 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围注册
公开(公告)号：WO2014004151A2
公开(公告)日：2014-01-03
申请号：PCT/US2013/046169
申请日：2013-06-17
申请人： INTEL CORPORATION , HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
发明人： HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
IPC分类号： G06F12/08
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

6. 发明申请

WO2013002789A1 METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS 审中-公开
标题翻译：用于内容加密的方法和装置，具有完整的检查和防止重复攻击的保护
公开(公告)号：WO2013002789A1
公开(公告)日：2013-01-03
申请号：PCT/US2011/042413
申请日：2011-06-29
申请人： INTEL CORPORATION , GUERON, Shay , SAVAGAONKAR, Uday , MCKEEN, Francis X. , ROZAS, Carlos V. , DURHAM, David M. , DOWECK, Jacob , MULLA, Ofir , ANATI, Ittai , GREENFIELD, Zvika , MAOR, Moshe
发明人： GUERON, Shay , SAVAGAONKAR, Uday , MCKEEN, Francis X. , ROZAS, Carlos V. , DURHAM, David M. , DOWECK, Jacob , MULLA, Ofir , ANATI, Ittai , GREENFIELD, Zvika , MAOR, Moshe
IPC分类号： G06F21/24 , G06F21/02 , G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/00 , G06F21/64 , H04L9/0637 , H04L9/3242
摘要： A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a "time stamp" indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a "time stamp" indicator associated with the cache line. The "time stamp indicator" is stored in a processor.
摘要翻译：提供了一种提供加密完整性检查和重放保护以防止对系统存储器的硬件攻击的方法和装置。分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。基于树的重放保护方案使用标准的XTS-AES来加密系统内存中的高速缓存行的内容。高速缓存行的消息认证码（MAC）使用增强型XTS-AES和与高速缓存行相关联的“时间戳”指示符进行加密。 “时间戳指示符”存储在处理器中。

7. 发明公开

EP2798769A1 PREVENTING PATTERN RECOGNITION IN ELECTRONIC CODE BOOK ENCRYPTION 有权
标题翻译： DER ELEKTRONISCHENCODEBUCHVERSCHLÜSSELUNG的VERHINDERUNG VON MUSTERERKENNUNG
公开(公告)号：EP2798769A1
公开(公告)日：2014-11-05
申请号：EP11878504.7
申请日：2011-12-30
申请人： Intel Corporation
发明人： JANUS, Scott , MARTIN, Jason , SAVAGAONKAR, Uday
IPC分类号： H04L9/06 , G06F21/60
CPC分类号： H04L9/0637 , G06F21/6209 , G06T1/20 , H04L2209/08 , H04N1/4486
摘要： In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
摘要翻译：通常，在一个方面，将噪声注入到要显示在显示器上的内容相关联的位图中以产生噪声位图。嘈杂的位图使用电子代码簿（ECB）加密进行加密。所得到的密文不包含来自内容的可识别的模式，如ECB加密的典型代码。噪声的注入可以包括修改位图中的至少像素子集的像素值。可以通过使用计数器，已知修改模式或随机数生成器来修改像素值。可以分析位图以确定如何修改位图以最大化位图的随机性，同时确保在呈现时视觉上感觉上相似的嘈杂位图。在块被加密之前，可以将噪声注入到像素块中。

8. 发明申请

WO2013101185A1 PREVENTING PATTERN RECOGNITION IN ELECTRONIC CODE BOOK ENCRYPTION 审中-公开
标题翻译：防止电子代码加密中的图案识别
公开(公告)号：WO2013101185A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068108
申请日：2011-12-30
申请人： INTEL CORPORATION , JANUS, Scott , MARTIN, Jason , SAVAGAONKAR, Uday
发明人： JANUS, Scott , MARTIN, Jason , SAVAGAONKAR, Uday
IPC分类号： H04L9/06 , G06F21/24
CPC分类号： H04L9/0637 , G06F21/6209 , G06T1/20 , H04L2209/08 , H04N1/4486
摘要： In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
摘要翻译：通常，在一个方面，将噪声注入到与将要呈现在显示器上的内容相关联的位图中以产生噪声位图。噪声位图使用电子代码簿（ECB）加密进行加密。所得到的密文不包括来自内容的可识别模式，如ECB加密典型。噪声的注入可以包括修改位图中的至少像素子集的像素值。可以通过使用计数器，已知修改模式或随机数生成器来修改像素值。可以分析位图以确定位图如何被修改以使位图的随机性最大化，同时确保在呈现时视觉上感觉上类似的噪声位图。在块被加密之前，可以将噪声注入到像素块中。

9. 发明申请

WO2013100965A1 A LOW-OVERHEAD CRYPTOGRAPHIC METHOD AND APPARATUS FOR PROVIDING MEMORY CONFIDENTIALITY, INTEGRITY AND REPLAY PROTECTION 审中-公开
标题翻译：提供记忆保密，完整性和重复保护的低成本克隆方法和设备
公开(公告)号：WO2013100965A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067590
申请日：2011-12-28
申请人： INTEL CORPORATION , CHHABRA, Siddhartha , SAVAGAONKAR, Uday , ROZAS, Carlos , NARENDRA TRIVEDI, Alpa , LONG, Men , DURHAM, David
发明人： CHHABRA, Siddhartha , SAVAGAONKAR, Uday , ROZAS, Carlos , NARENDRA TRIVEDI, Alpa , LONG, Men , DURHAM, David
IPC分类号： G06F21/20 , G06F21/24
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/00 , G06F21/77
摘要： A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.
摘要翻译：一种提供低开销加密方案的方法和系统，其通过去除加密树的各个级别之间的关键读后依赖关系来提供内存机密性，完整性和重放保护。在本发明的一个实施例中，子节点的密码处理可以与母节点的密码处理流水线化。由本发明提供的这种并行化导致密码流水线的有效利用，能够显着降低性能开销。

10. 发明申请

WO2013100964A1 METHOD AND SYSTEM FOR PROTECTING MEMORY INFORMATION IN A PLATFORM 审中-公开
标题翻译：保护平台内存信息的方法和系统
公开(公告)号：WO2013100964A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067586
申请日：2011-12-28
申请人： INTEL CORPORATION , NARENDRA TRIVEDI, Alpa , DURHAM, David , LONG, Men , CHHABRA, Siddhartha , SAVAGAONKAR, Uday , ROZAS, Carlos
发明人： NARENDRA TRIVEDI, Alpa , DURHAM, David , LONG, Men , CHHABRA, Siddhartha , SAVAGAONKAR, Uday , ROZAS, Carlos
IPC分类号： G06F21/20 , G06F21/24
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/78 , G06F21/79 , H04L9/0643 , H04L2209/12
摘要： A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on "Global and Local Counters". This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the "tweak" used in the XTS encryption without sacrificing cryptographic strength.
摘要翻译：一种方法和系统，为存储在存储器中的敏感信息提供有效，可扩展且低成本的保密性，完整性和重放保护解决方案，并防止攻击者观察和/或修改系统的状态。在本发明的一个实施例中，系统通过经由XTS调整加密模式对其存储器内容具有强大的硬件保护，其中基于“全局和本地计数器”导出调整。该方案提供了通过允许多个计数器级别为任何大小的存储器提供芯片区域高效的重放保护，并有助于使用小型计数器来导出XTS加密中使用的“调整”，而不会牺牲加密强度。

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