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1. 发明申请

WO2019040050A1 APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE 审中-公开
公开(公告)号：WO2019040050A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/048059
申请日：2017-08-22
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , AIZIK, Yoni , NATANZON, Esfir , ROSENZWEIG, Nir , SHULMAN, Nadav , PLACKLE, Bart
IPC分类号： G06F1/32 , G06F9/50
摘要： Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

2. 发明申请

WO2016105677A1 SYSTEM MAXIMUM CURRENT PROTECTION 审中-公开
标题翻译：系统最大电流保护
公开(公告)号：WO2016105677A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/059762
申请日：2015-11-09
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , ROSENZWEIG, Nir , RAJWAN, Doron , SHULMAN, Nadav , LEIBOVICH, Gal , ZIV, Tomer , GABAI, Amit , RODRIGUEZ, Jorge P. , CARLSON, Jeffrey A.
IPC分类号： G06F1/28 , G06F1/26
CPC分类号： G06F1/324 , G05F1/10 , G06F1/28 , G06F1/3206 , H03L7/08 , Y02D10/126
摘要： A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
摘要翻译：一种用于提供主动电流保护的方法和装置。在一个实施例中，该方法包括：在转换到集成电路（IC）的新状态之前，通过针对多个域中的每个域计算预期电流来计算IC中多个域的预期功率之和在新状态的单个域频率上，将预期电流与其相关联的电压乘以用于新状态的多个域中的每一个; 将总和与功率限制进行比较; 并且如果所述和大于所述功率极限，则减少与所述多个域中的至少一个域相关联的各个域频率，以将所述IC的总瞬时功率维持在所述功率极限以下。

3. 发明申请

WO2019005392A1 SYSTEM, APPARATUS AND METHOD FOR LOOSE LOCK-STEP REDUNDANCY POWER MANAGEMENT 审中-公开
公开(公告)号：WO2019005392A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/035042
申请日：2018-05-30
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , ROSENZWEIG, Nir , AIZIK, Yoni
IPC分类号： G06F1/32 , G06F11/16
摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

4. 发明申请

WO2016191032A1 CONTROLLING PERFORMANCE STATES OF PROCESSING ENGINES OF A PROCESSOR 审中-公开
标题翻译：控制处理器处理发动机的性能状态
公开(公告)号：WO2016191032A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/029923
申请日：2016-04-29
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROTEM, Efraim , ABU SALAH, Hisham , AIZIK, Yoni , RAJWAN, Doron , ROSENZWEIG, Nir , LEIBOVICH, Gal , SABIN, Yevgeni , LEVY, Shay
IPC分类号： G06F1/32 , G06F9/28
CPC分类号： G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个平均主动处理引擎数。描述和要求保护其他实施例。

5. 发明申请

WO2016007219A1 PROCESSOR STATE CONTROL BASED ON DETECTION OF PRODUCER/CONSUMER WORKLOAD SERIALIZATION 审中-公开
标题翻译：基于检测生产者/消费者工作流程序列化的处理器状态控制
公开(公告)号：WO2016007219A1
公开(公告)日：2016-01-14
申请号：PCT/US2015/030928
申请日：2015-05-15
申请人： INTEL CORPORATION
发明人： THERIEN, Guy, M. , RAJWAN, Doron
IPC分类号： G06F9/48 , G06F13/42
CPC分类号： G06F1/08 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for controlling the processor state (e.g., the clock frequency) of processors based on detection of producer/consumer workload serialization across the processors. The system may include a utilization measurement module configured to measure utilization of the processors. The system may also include a correlation module configured to estimate a balance between producer/consumer (P/C) workload and non-P/C workload executing on the processors. The system may further include a clock frequency adjustment module configured to calculate a clock frequency adjustment based on the estimated balance and the measured utilization and to update the clock frequency of the processors based on the calculated adjustment.
摘要翻译：通常，本公开提供了用于基于对跨处理器的生产者/消费者工作负载序列化的检测来控制处理器的处理器状态（例如，时钟频率）的系统，设备，方法和计算机可读介质。系统可以包括被配置为测量处理器的利用率的利用率测量模块。该系统还可以包括被配置为估计生产者/消费者（P / C）工作负荷与在处理器上执行的非P / C工作负载之间的平衡的相关模块。该系统还可以包括时钟频率调整模块，该时钟频率调整模块被配置为基于所估计的平衡和所测量的利用率来计算时钟频率调整，并且基于所计算的调整来更新处理器的时钟频率。

6. 发明申请

WO2017222690A1 CONTROLLING FORCED IDLE STATE OPERATION IN A PROCESSOR 审中-公开
标题翻译：在处理器中控制强制空闲状态操作
公开(公告)号：WO2017222690A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/033253
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROTEM, Efraim , AIZIK, Yoni , RAJWAN, Doron , LEIBOVICH, Gal , SHULMAN, Nadav , ABU SALAH, Hisham
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/266 , G06F13/24 , Y02D10/14
摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和功率控制器，功率控制器包括第一逻辑，响应于确定处理器处于强制空闲状态少于阈值持续时间，以更新第一计数器，并且响应于超过控制阈值的第一计数器的值，防止处理器进入强制空闲状态。描述并要求保护其他实施例。

7. 发明申请

WO2017176358A1 SYSTEM POWER MANAGEMENT 审中-公开
标题翻译：系统电源管理
公开(公告)号：WO2017176358A1
公开(公告)日：2017-10-12
申请号：PCT/US2017/016732
申请日：2017-02-06
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , SCHIFF, Tod F , RAJWAN, Doron , JULL, Jeffrey M. , HERMERDING II, James G , ROSENZWEIG, Nir , TOLEDANO, Maytal , UAN-ZO-LI, Alexander B
IPC分类号： G06F1/32 , G05B23/02
摘要： One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.
摘要翻译：一个实施例提供了一种装置。该装置包括功率控制逻辑和关键比较器。功率控制逻辑至少部分地基于可用输入功率值（Pin）来确定临界阈值（TC）。关键比较器是比较系统功耗值（Psys）和临界阈值，并在系统功耗值大于或等于临界阈值时向处理器断言处理器关键节流信号。

8. 发明申请

WO2013095869A1 A METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING AUTONOMOUS HARDWARE-BASED DEEP POWER DOWN IN DEVICES 审中-公开
标题翻译：一种用于能源效率和能源保护的方法，装置和系统，包括基于自动硬件的深度下降的设备
公开(公告)号：WO2013095869A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/066557
申请日：2012-11-26
申请人： INTEL CORPORATION
发明人： SODHI, Inder M. , NAVEH, Alon , RAJWAN, Doron , WELLS, Ryan D. , SAMSON, Eric D.
IPC分类号： G06F1/32
CPC分类号： G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
摘要翻译：描述了能量效率和能量节约的系统，装置和方法的实施例，包括实现设备的自主的基于硬件的深度断电。在一个实施例中，系统包括与设备和静态存储器耦合的设备，静态存储器和功率控制单元。该系统还包括功率控制单元的深度掉电逻辑，用于监视设备的状态，并且当设备空闲时将设备传送到深度断电状态。在系统中，当处于深功率关闭状态时，器件消耗的功率小于空闲状态。

9. 发明授权

EP3353653B1 TECHNIQUES FOR FLEXIBLE AND DYNAMIC FREQUENCY-RELATED TELEMETRY 有权
公开(公告)号：EP3353653B1
公开(公告)日：2020-07-15
申请号：EP16849156.1
申请日：2016-07-22
申请人： Intel Corporation
发明人： RAJWAN, Doron , WEISSMANN, Eliezer , AIZIK, Yoni , FEIT, Itai , KUZI, Tal , ZIV, Tomer , SHULMAN, Nadav
IPC分类号： G06F9/48 , G06F1/32 , G06F11/30 , G06F1/3206 , G06F11/34

10. 发明申请

WO2018063752A1 MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL 审中-公开
标题翻译：用于计算机处理器控制的多级磁盘
公开(公告)号：WO2018063752A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050044
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： RAJWAN, Doron , ROTEM, Efraim , WEISSMANN, Eliezer , ANANTHAKRISHNAN, Avinash N. , SHAPIRA, Dorit
IPC分类号： G06F13/16
CPC分类号： G06F1/3228 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3293 , G06F17/5054 , G06F2217/78 , G06F2217/80
摘要： In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括处理核心和中央控制单元，以便：同时执行外部控制回路和内部控制回路，其中外部控制回路将整体监视处理器并且其中所述内部控制回路将监视包括在所述处理器中的第一处理核心; 基于外部控制回路确定包括在处理器中的第一处理核的第一控制动作; 基于所述内部控制回路确定所述处理器中包括的所述第一处理核心的第二控制动作; 基于所述第一控制动作和所述第二控制动作的比较，选择所述第一控制动作和所述第二控制动作中的一个作为选择的控制动作; 并将选择的控制动作应用于第一处理核心。描述并要求保护其他实施例。

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