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1. 发明申请

WO2021011577A1 DYNAMIC ENERGY PERFORMANCE PREFERENCE BASED ON WORKLOADS USING AN ADAPTIVE ALGORITHM 审中-公开
公开(公告)号：WO2021011577A1
公开(公告)日：2021-01-21
申请号：PCT/US2020/042014
申请日：2020-07-14
申请人： INTEL CORPORATION
发明人： SAKARDA, Premanand , ROTEM, Efraim , WEISSMANN, Eliezer , ABU SALAH, Hisham , BEJA, Hadas , FENGER, Russell , GANAPATHY, Deepak , HERMERDING II, James , KARAVANY, Ido , KRISHNAKUMAR, Nivedha , NAIR, Sudheer , OLSWANG, Gilad , PERI, Moran , WAGNER, Avishai , WANG, Zhongsheng , YASSIN, Noha
IPC分类号： G06F1/324 , G06F1/3212 , G06F1/3296 , G06F1/3293 , G06N20/00
摘要： Described are mechanisms and methods for tracking user behavior profile over large time intervals and extracting observations for a user usage profile. The mechanisms and methods use machine learning (ML) algorithms embedded into a dynamic platform and thermal framework (DPTF) (e.g., Dynamic Tuning Technology) and predict device workloads using hardware (HW) counters. These mechanisms and methods may accordingly increase performance and user responsiveness by dynamically changing an Energy Performance Preference (EPP) based on a longer time workload analysis and workload prediction.

2. 发明申请

WO2018026527A1 PROVIDING AN INTERFACE FOR DEMOTION CONTROL INFORMATION IN A PROCESSOR 审中-公开
标题翻译：为处理器中的解决控制信息提供接口
公开(公告)号：WO2018026527A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/042999
申请日：2017-07-20
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROSENZWEIG, Nir , ROTEM, Efraim , BEN-RAPHAEL, Yoav , NAVEH, Alon
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个核心; 功率控制器，所述功率控制器包括逻辑，以自主降级对所述多个核心中的至少一个核心的第一请求以进入第一低功率状态，以使所述至少一个核心进入第二低功率状态，所述第一低功率状态比第二低功率状态更深的低功率状态; 以及用于接收来自系统软件的输入的接口，所述输入包括至少一个降级控制参数，其中所述逻辑至少部分地基于所述至少一个降级控制参数来自主降级所述第一请求。描述并要求保护其他实施例。

3. 发明申请

WO2017222690A1 CONTROLLING FORCED IDLE STATE OPERATION IN A PROCESSOR 审中-公开
标题翻译：在处理器中控制强制空闲状态操作
公开(公告)号：WO2017222690A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/033253
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROTEM, Efraim , AIZIK, Yoni , RAJWAN, Doron , LEIBOVICH, Gal , SHULMAN, Nadav , ABU SALAH, Hisham
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/266 , G06F13/24 , Y02D10/14
摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和功率控制器，功率控制器包括第一逻辑，响应于确定处理器处于强制空闲状态少于阈值持续时间，以更新第一计数器，并且响应于超过控制阈值的第一计数器的值，防止处理器进入强制空闲状态。描述并要求保护其他实施例。

4. 发明申请

WO2017176358A1 SYSTEM POWER MANAGEMENT 审中-公开
标题翻译：系统电源管理
公开(公告)号：WO2017176358A1
公开(公告)日：2017-10-12
申请号：PCT/US2017/016732
申请日：2017-02-06
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , SCHIFF, Tod F , RAJWAN, Doron , JULL, Jeffrey M. , HERMERDING II, James G , ROSENZWEIG, Nir , TOLEDANO, Maytal , UAN-ZO-LI, Alexander B
IPC分类号： G06F1/32 , G05B23/02
摘要： One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.
摘要翻译：一个实施例提供了一种装置。该装置包括功率控制逻辑和关键比较器。功率控制逻辑至少部分地基于可用输入功率值（Pin）来确定临界阈值（TC）。关键比较器是比较系统功耗值（Psys）和临界阈值，并在系统功耗值大于或等于临界阈值时向处理器断言处理器关键节流信号。

5. 发明申请

WO2017052878A1 INTEGRATING A POWER ARBITER IN A PROCESSOR 审中-公开
标题翻译：在处理器中集成一个功率控制器
公开(公告)号：WO2017052878A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/047991
申请日：2016-08-22
申请人： INTEL CORPORATION
发明人： GANOR, Assaf , ROTEM, Efraim , WINER, Noam , VIKINSKI, Omer
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G05F1/46 , G06F1/18
摘要： In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：功率切换器电路，用于接收第一电压，并且对第一相中的第一电压进行至少一个电荷存储装置的充电并在第二相中输出电荷; 耦合到所述功率开关电路的选择电路，以响应于控制信号将所述输出电荷耦合到多个负载电路中的所选择的一个; 以及控制电路，用于至少部分地基于耦合到所选择的负载电路的轨道的反馈电压与参考电压的比较来产生控制信号。描述和要求保护其他实施例。

6. 发明申请

WO2012129147A2 MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中管理功耗
公开(公告)号：WO2012129147A2
公开(公告)日：2012-09-27
申请号：PCT/US2012/029604
申请日：2012-03-19
申请人： INTEL CORPORATION , FETZER, Eric , REIDLINGER, Reid J. , SOLTIS, Don , BOWHILL, William J. , SHRIMALI, Satish , SISTLA, Krishnakanth , ROTEM, Efraim , KUMAR, Rakesh , GARG, Vivek , NAVEH, Alon , SHARMA, Lokesh
发明人： FETZER, Eric , REIDLINGER, Reid J. , SOLTIS, Don , BOWHILL, William J. , SHRIMALI, Satish , SISTLA, Krishnakanth , ROTEM, Efraim , KUMAR, Rakesh , GARG, Vivek , NAVEH, Alon , SHARMA, Lokesh
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译：处理器可以包括核心和无孔区域。可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。结果，可以减少由无孔区域消耗的空闲功率。

7. 发明申请

WO2008073597A1 METHOD AND APPARATUS OF POWER MANAGEMENT OF PROCESSOR 审中-公开
标题翻译：处理器功率管理方法与装置
公开(公告)号：WO2008073597A1
公开(公告)日：2008-06-19
申请号：PCT/US2007/082959
申请日：2007-10-30
申请人： INTEL CORPORATION , ROTEM, Efraim , AGGARWAL, Anil , FENGER, Russell
发明人： ROTEM, Efraim , AGGARWAL, Anil , FENGER, Russell
IPC分类号： G06F9/50
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.
摘要翻译：简而言之，是一种处理器和一种设置turbo模式使能处理器的性能状态的方法。该方法包括在预定时间段内确定有效性能状态，在预定时间段内基于核心利用率和有效性能状态计算目标性能状态，并将启用turbo模式的处理器设置为turbo模式执行状态。

8. 发明申请

WO2019005392A1 SYSTEM, APPARATUS AND METHOD FOR LOOSE LOCK-STEP REDUNDANCY POWER MANAGEMENT 审中-公开
公开(公告)号：WO2019005392A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/035042
申请日：2018-05-30
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , ROSENZWEIG, Nir , AIZIK, Yoni
IPC分类号： G06F1/32 , G06F11/16
摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

9. 发明申请

WO2016191032A1 CONTROLLING PERFORMANCE STATES OF PROCESSING ENGINES OF A PROCESSOR 审中-公开
标题翻译：控制处理器处理发动机的性能状态
公开(公告)号：WO2016191032A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/029923
申请日：2016-04-29
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROTEM, Efraim , ABU SALAH, Hisham , AIZIK, Yoni , RAJWAN, Doron , ROSENZWEIG, Nir , LEIBOVICH, Gal , SABIN, Yevgeni , LEVY, Shay
IPC分类号： G06F1/32 , G06F9/28
CPC分类号： G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个平均主动处理引擎数。描述和要求保护其他实施例。

10. 发明申请

WO2015099791A1 POWER MONITOR FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备用电源监控器
公开(公告)号：WO2015099791A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/078121
申请日：2013-12-27
申请人： INTEL CORPORATION , MA, Ruoying Mary , HERMERDING II, James G. , ROTEM, Efraim , RODRIGUEZ, Jorge P. , CARLSON, Jeffrey A
发明人： MA, Ruoying Mary , HERMERDING II, James G. , ROTEM, Efraim , RODRIGUEZ, Jorge P. , CARLSON, Jeffrey A
IPC分类号： G06F1/28
CPC分类号： G06F1/3262 , G06F1/3206 , G06F1/3212 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： An electronic device comprising: a power monitor to receive system power to be delivered to a processor and to one or more components of a system, the power monitor to provide information corresponding to the system power, and a processor to change a performance of the processor based at least in part on the information corresponding to the system power.
摘要翻译：一种电子设备，包括：功率监视器，用于接收要传送到处理器和系统的一个或多个组件的系统功率，所述功率监视器提供对应于系统功率的信息，以及处理器，以改变处理器的性能至少部分地基于对应于系统功率的信息。

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