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1. 发明申请

WO2020190812A1 COMPUTE OPTIMIZATION IN GRAPHICS PROCESSING 审中-公开
公开(公告)号：WO2020190812A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022850
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： RANGANATHAN, Vasanth , APPU, Abhishek R. , ASHBAUGH, Ben , DOYLE, Peter , FLIFLET, Brandon , HUNTER, Arthur , INSKO, Brent , JANUS, Scott , KOKER, Altug , NAVALE, Aditya , RAY, Joydeep , SINHA, Kamal , STRIRAMASSARMA, Lakshminarayanan , SURTI, Prasoonkumar , VALERIO, James
IPC分类号： G06F9/50
摘要： Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.

2. 发明申请

WO2017205002A1 HIERARCHICAL LOSSLESS COMPRESSION AND NULL DATA SUPPORT 审中-公开
标题翻译：分层无损压缩和NULL数据支持
公开(公告)号：WO2017205002A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/030323
申请日：2017-04-30
申请人： INTEL CORPORATION
发明人： SEILER, Larry , SURTI, Prasoonkumar , NAVALE, Aditya
IPC分类号： G06T9/00 , G06T1/20 , G06T1/60
摘要： Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.
摘要翻译：这里描述的是计算机图形技术，以促进对包括纹理图的存储器块进行有效且高效的存储器处理。更具体地说，本文描述的一个或多个实施方式有利于对存储器资源（包括纹理图）的空数据支持的存储器的分层无损压缩。更特别地，这里描述的一个或多个实施方式促进了用于无损压缩的元数据的使用以及对于平铺资源的空编码的支持。该技术还允许使用快速清除压缩方法，其中元数据指定整个访问应返回一些指定的明确值。

3. 发明申请

WO2013074124A1 SCALABLE GEOMETRY PROCESSING WITHIN A CHECKERBOARD MULTI-GPU CONFIGURATION 审中-公开
标题翻译：在检查板多GPU配置中进行可扩展的几何处理
公开(公告)号：WO2013074124A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/061447
申请日：2011-11-18
申请人： INTEL CORPORATION , DOYLE, Peter L. , BOLES, Jeffery S. , HUNTER, Arthur D, Jr. , KOKER, Altug , NAVALE, Aditya
发明人： DOYLE, Peter L. , BOLES, Jeffery S. , HUNTER, Arthur D, Jr. , KOKER, Altug , NAVALE, Aditya
IPC分类号： G06F13/14 , G06F15/80
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
摘要翻译：描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器的核心，并将几何设置处理结果存储在本地存储中。然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果和至少一个其他处理器核心的本地存储来执行光栅化。

4. 发明申请

WO2004063916A3 MEMORY CONTROLLER CONSIDERING PROCESSOR POWER STATES 审中-公开
公开(公告)号：WO2004063916A3
公开(公告)日：2004-07-29
申请号：PCT/US2004/000092
申请日：2004-01-02
申请人： INTEL CORPORATION
发明人： SAMSON, Eric , NAVALE, Aditya , JENSEN, Sam , SRITANYARATANA, Siripong , CHENG, Win
IPC分类号： G06F1/32
摘要： When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

5. 发明申请

WO2014014628A1 PERFORMING SCHEDULING OPERATIONS FOR GRAPHICS HARDWARE 审中-公开
标题翻译：执行图形硬件的调度操作
公开(公告)号：WO2014014628A1
公开(公告)日：2014-01-23
申请号：PCT/US2013/047638
申请日：2013-06-25
申请人： INTEL CORPORATION , VEMBU, Balaji , NAVALE, Aditya , RAMADOSS, Murali , STANDRING, David, I. , BALA, Kritika
发明人： VEMBU, Balaji , NAVALE, Aditya , RAMADOSS, Murali , STANDRING, David, I. , BALA, Kritika
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , Y02D10/24
摘要： A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
摘要翻译：本文描述了用于执行图形硬件的调度操作的计算设备。计算设备包括被配置为执行应用的中央处理单元（CPU）。计算设备还包括被配置为独立于CPU操作的图形调度器。图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。

6. 发明申请

WO2013187862A1 A FAST MECHANISM FOR ACCESSING 2n±1 INTERLEAVED MEMORY SYSTEM 审中-公开
标题翻译：用于访问2n±1个交互式存储器系统的快速机制
公开(公告)号：WO2013187862A1
公开(公告)日：2013-12-19
申请号：PCT/US2012/041855
申请日：2012-06-11
申请人： INTEL CORPORATION , SHARMA, Saurabh , KOKER, Altug , NAVALE, Aditya
发明人： SHARMA, Saurabh , KOKER, Altug , NAVALE, Aditya
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0607 , G06F2212/302
摘要： A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2 n + 1) or (2 n 1), n being a positive integer number. Upon receiving an address N , the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M . The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.
摘要翻译：由控制器实现的机制使得能够有效地访问包括M个模块的交错存储器系统，M是（2n + 1）或（2n 1），n是正整数。在接收到地址N时，控制器执行移位和加/减操作，以基于N在M的二项式系列展开来获得N除以M的商。控制器基于商来计算N的余数除以M。然后，控制器基于剩余部分访问存储器中的一个模块。

7. 发明申请

WO2008005722A1 AN APPARATUS AND METHOD FOR MEMORY ADDRESS RE-MAPPING OF GRAPHICS DATA 审中-公开
标题翻译：用于存储器地址重新映射图形数据的装置和方法
公开(公告)号：WO2008005722A1
公开(公告)日：2008-01-10
申请号：PCT/US2007/071953
申请日：2007-06-22
申请人： INTEL CORPORATION , VEMBU, Balaji , NAVALE, Aditya , GANDHI, Wishwesh A.
发明人： VEMBU, Balaji , NAVALE, Aditya , GANDHI, Wishwesh A.
IPC分类号： G06F12/02 , G06F13/28 , G06T1/00
CPC分类号： G06F12/1009 , G06F9/4401 , G06F9/4403 , G06F9/4411 , G06F9/45533 , G06F9/45558 , G06F12/109 , G06F13/28 , G06F2009/45579 , G06F2009/45583 , G06F2212/152 , G06T1/60
摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.
摘要翻译：一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为支持虚拟机。可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影像表条目的GPA转换为HPA。

8. 发明申请

WO2006019636A1 METHOD AND APPARATUS FOR DYNAMIC DLL POWERDOWN AND MEMORY SELF-REFRESH 审中-公开
标题翻译：用于动态DLL功耗和存储器自刷新的方法和装置
公开(公告)号：WO2006019636A1
公开(公告)日：2006-02-23
申请号：PCT/US2005/024375
申请日：2005-07-08
申请人： INTEL CORPORATION , SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
发明人： SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
IPC分类号： G06F1/32
CPC分类号： G06F1/3225
摘要： Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.
摘要翻译：本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。特别地，本发明的实施例将自刷新和芯片组时钟电路中的存储器动态地放置在掉电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

9. 发明申请

WO2014209721A1 MID COMMAND BUFFER PREEMPTION FOR GRAPHICS WORKLOADS 审中-公开
标题翻译：图形工作负载的MID命令缓冲区预处理
公开(公告)号：WO2014209721A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/042972
申请日：2014-06-18
申请人： INTEL CORPORATION
发明人： NALLURI, Hema Chand , NAVALE, Aditya , RAMADOSS, Murali , BOLES, Jeffery S.
IPC分类号： G06F9/46
CPC分类号： G06T1/60 , G06F9/48 , G06F9/485 , G06T1/20
摘要： Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.
摘要翻译：图形处理环境中的图形工作负载描述了中间命令缓冲区抢占。在一个示例中，在图形处理器处执行第一上下文的指令，第一上下文在可寻址缓冲器中具有指令序列，并且指令中的至少一个是抢占指令。在执行抢占指令之后，在指令序列完成之前停止第一上下文的执行。存储用于第一上下文将被恢复的指令的地址。执行第二上下文，并且在完成第二上下文的执行时，在存储的地址处恢复执行第一上下文。

10. 发明申请

WO2014088726A1 MEMORY BASED SEMAPHORES 审中-公开
标题翻译：基于记忆的SEMAPHORES
公开(公告)号：WO2014088726A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/067076
申请日：2013-10-28
申请人： INTEL CORPORATION
发明人： NALLURI, Hema Chand , NAVALE, Aditya
IPC分类号： G06F9/38
CPC分类号： G06T1/20 , G06F9/48 , G06F9/52 , G06F15/167 , G09G5/001
摘要： Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register.
摘要翻译：描述了基于内存的信号量，其用于在不同处理引擎之间同步操作。在一个示例中，操作包括在生成器引擎处执行上下文，执行包括更新存储器寄存器，以及将生成器引擎的信号发送到已更新存储器寄存器的消费者引擎，该信号包括识别的上下文ID 由消费者引擎执行以更新寄存器的上下文。

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