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1. 发明专利

GB2520870A Apparatus and method for determining the number of execution cores to keep active in a processor 未知
公开(公告)号：GB2520870A
公开(公告)日：2015-06-03
申请号：GB201502690
申请日：2013-06-25
申请人： INTEL CORP , ANANTHAKRISHNAN AVINASH N , JULIEN SEBOT , SCHWARTZ JAY D , GUNTHER STEPHEN H , SAMSON ERIC , SAMSON ERIC
发明人： ANANTHAKRISHNAN AVINASH N , SEBOT JULIEN FEFE , SCHWARTZ JAY D , GUNTHER STEPHEN H , SAMSON ERIC
IPC分类号： G06F1/26 , G06F1/32 , G06F9/38 , G06F9/46
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

2. 发明专利

CA2349153A1 METHOD FOR MODELING THE TRANSPORT OF IONS IN HYDRATED CEMENTSYSTEMS 未知
公开(公告)号：CA2349153A1
公开(公告)日：2002-11-24
申请号：CA2349153
申请日：2001-05-24
申请人： SAMSON ERIC , MALTAIS YANNICK , MARCHAND JACQUES
发明人： SAMSON ERIC , MALTAIS YANNICK , MARCHAND JACQUES
IPC分类号： G01N27/416 , G01N33/38 , G01N27/26
摘要： -50- The present invention relates to a computational tool that allows to evaluat e the degradation of cement-based materials under various types of chemical attack s such as sulfates, chloride, and plain water. It is based on the physical principles of ionic mass conservation and chemical equilibrium between a solution and different solid phases. The effect of the dissolution or the precipitation of solid phases on the transport coefficients is considered. A method for determining an ion concentration in solution of at least two ions capable of undergoing transport in a cement-based material under a chemical attack and a solid phase profile for at least one component of said cement- based material is provided. A method for determining a diffusion coefficient for each of at least two ions capable of undergoing transport in a cement-based material is also provided.

3. 发明专利

CA2349153C METHOD FOR MODELING THE TRANSPORT OF IONS IN HYDRATED CEMENTSYSTEMS 未知
公开(公告)号：CA2349153C
公开(公告)日：2007-08-14
申请号：CA2349153
申请日：2001-05-24
申请人： MARCHAND JACQUES , SAMSON ERIC , MALTAIS YANNICK
发明人： MARCHAND JACQUES , SAMSON ERIC , MALTAIS YANNICK
IPC分类号： G01N33/38 , G01N13/00 , G01N15/00 , G01N27/416
摘要： The present invention relates to a computational tool that allows to evaluat e the degradation of cement-based materials under various types of chemical attack s such as sulfates, chlorides, and plain water. It is based on the physical principles of ionic mass conservation and chemical equilibrium between a solution and different solid phases. The effect of the dissolution or the precipitation of solid phases on the transport coefficients is considered. A method for determining an ion concentration in solution of at least two ions capable of undergoing transport in a cement-based material under a chemical attack and a solid phase profile for at least one component of said cement- based material is provided. A method for determining a diffusion coefficient for each of at least two ions capable of undergoing transport in a cement-based material is also provided.

4. 发明专利

GB201502690D0 Apparatus and method for determining the number of execution cores to keep active in a processor 未知
公开(公告)号：GB201502690D0
公开(公告)日：2015-04-01
申请号：GB201502690
申请日：2013-06-25
申请人： INTEL CORP AND SEBOT JULIEN AND ANANTHAKRISHNAN AVINASH N AND SAMSON ERIC AND SCHWARTZ JAY D AND GUN
摘要： A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.

5. 发明申请

WO2013105913A2 ADAPTIVE FRAME RATE CONTROL FOR A GRAPHICS SUBSYSTEM 审中-公开
标题翻译：图形子系统的自适应帧速率控制
公开(公告)号：WO2013105913A2
公开(公告)日：2013-07-18
申请号：PCT/US2011/062501
申请日：2011-11-30
申请人： INTEL CORPORATION , RAMADOSS, Murali , SAMSON, Eric
发明人： RAMADOSS, Murali , SAMSON, Eric
IPC分类号： G06F9/06 , G06F13/14 , G06T1/00
CPC分类号： G06T1/20 , G06F1/324 , G06F1/3265 , G06F3/14 , G06T1/60 , G09G5/18 , G09G2330/021 , G09G2340/0435 , Y02D10/126 , Y02D10/153 , Y02D50/20
摘要： Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.
摘要翻译：公开了用于基于平均帧速率与目标帧速率的比较以及还基于图形子系统是否处于图像子系统和/或处理器的性能状态来调整图形子系统和/或处理器的性能状态的示例突发模式或持续操作模式。

6. 发明申请

WO2006072097A3 METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL 审中-公开
公开(公告)号：WO2006072097A3
公开(公告)日：2006-07-06
申请号：PCT/US2005/047677
申请日：2005-12-29
申请人： INTEL CORPORATION , SAMSON, Eric , HORIGAN, John , JACKSON, Robert , THAKKAR, Shreekant
发明人： SAMSON, Eric , HORIGAN, John , JACKSON, Robert , THAKKAR, Shreekant
IPC分类号： G06F1/20
摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.

7. 发明申请

WO2014051780A1 APPARATUS AND METHOD FOR DETERMINING THE NUMBER OF EXECUTION CORES TO KEEP ACTIVE IN A PROCESSOR 审中-公开
标题翻译：用于确定处理器中执行线数量保持有效的装置和方法
公开(公告)号：WO2014051780A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047629
申请日：2013-06-25
申请人： INTEL CORPORATION , ANANTHAKRISHNAN, Avinash N. , SEBOT, Julien Fefe , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SAMSON, Eric C.
发明人： ANANTHAKRISHNAN, Avinash N. , SEBOT, Julien Fefe , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SAMSON, Eric C.
IPC分类号： G06F1/26 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译：描述了包括多个执行核心的处理器。处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使得处理器以基本上线性的功率消耗与频率操作区域相互作用，使得作为功率消耗的功能的性能增益与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。

8. 发明申请

WO2013101829A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING NON FRAME AWARE FREQUENCY SELECTION 审中-公开
标题翻译：方法，装置和能源节能系统，包括非框架频率选择
公开(公告)号：WO2013101829A1
公开(公告)日：2013-07-04
申请号：PCT/US2012/071653
申请日：2012-12-26
申请人： INTEL CORPORATION , SAMSON, Eric, C.
发明人： SAMSON, Eric, C.
IPC分类号： G06F1/32 , G06F13/14 , G06F13/24
CPC分类号： G09G5/18 , G06F1/324 , G09G5/363 , G09G2310/08 , G09G2330/021 , G09G2360/02 , G09G2360/12
摘要： Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.
摘要翻译：调整图形控制器的频率的系统和方法可以包括确定与输入/输出（I / O）队列相关联的度量的逻辑。该度量可用于确定是否存在I / O限制条件。 I / O限制条件可能与图形控制器相关联。当存在I / O限制条件时，可能存在导致图形控制器的频率降低的逻辑，并且当I / O限制条件不存在时，导致图形控制器的频率增加的逻辑。当度量的大小等于或大于第一阈值时，可能存在I / O限制条件。当度量的大小等于或小于第二阈值时，I / O限制条件可能不存在。

9. 发明申请

WO2006072097A2 METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL 审中-公开
标题翻译：外部处理器热控制的方法和装置
公开(公告)号：WO2006072097A2
公开(公告)日：2006-07-06
申请号：PCT/US2005047677
申请日：2005-12-29
申请人： INTEL CORP , SAMSON ERIC , HORIGAN JOHN , JACKSON ROBERT , THAKKAR SHREEKANT
发明人： SAMSON ERIC , HORIGAN JOHN , JACKSON ROBERT , THAKKAR SHREEKANT
CPC分类号： G06F1/206
摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.
摘要翻译：公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。从属组件或主组件可以是中央处理单元，图形存储器和控制器集线器，或中央处理单元存储器控制器集线器。从组件可以发送第二信号以指示从组件的温度已超过其温度。然后，主组件将启动主组件的节流以降低计算系统的总体温度。主组件可以被节流到比从属组件小的程度。可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。可以通过图形用户界面从用户接收选择策略。选择策略可以基于由计算系统执行的动作。

10. 发明申请

WO2006019636A1 METHOD AND APPARATUS FOR DYNAMIC DLL POWERDOWN AND MEMORY SELF-REFRESH 审中-公开
标题翻译：用于动态DLL功耗和存储器自刷新的方法和装置
公开(公告)号：WO2006019636A1
公开(公告)日：2006-02-23
申请号：PCT/US2005/024375
申请日：2005-07-08
申请人： INTEL CORPORATION , SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
发明人： SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
IPC分类号： G06F1/32
CPC分类号： G06F1/3225
摘要： Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.
摘要翻译：本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。特别地，本发明的实施例将自刷新和芯片组时钟电路中的存储器动态地放置在掉电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

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