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1. 发明申请

WO2020190805A1 MULTI-TILE MEMORY MANAGEMENT 审中-公开
公开(公告)号：WO2020190805A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022843
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： APPU, Abhishek R. , KOKER, Altug , ANANTARAMAN, Aravindh , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , MACPHERSON, Mike , MAIYURAN, Subramaniam , RAY, Joydeep , STRIRAMASSARMA, Lakshminarayanan , JANUS, Scott , INSKO, Brent , RANGANATHAN, Vasanth , SINHA, Kamal , HUNTER, Arthur , SURTI, Prasoonkumar , PUFFER, David , VALERIO, James , SHAH, Ankur N.
IPC分类号： G06F12/0811 , G06F12/0875 , G06F16/27 , G06F12/0866 , G06F16/2453
摘要： Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

2. 发明申请

WO2020190801A1 GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY 审中-公开
公开(公告)号：WO2020190801A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022839
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： RAY, Joydeep , PANNEER, Selvakumar , TANGRI, Saurabh , ASHBAUGH, Ben , JANUS, Scott , APPU, Abhishek , GEORGE, Varghese , IYER, Ravishankar , JAIN, Nilesh , K, Pattabhiraman , KOKER, Altug , MACPHERSON, Mike , MASTRONARDE, Josh , OULD-AHMED-VALL, Elmoustapha , S, Jayakrishna P. , SAMSON, Eric
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/06
摘要： Embodiments described herein include, software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

3. 发明申请

WO2013089776A2 DRIVING MULTIPLE DISPLAYS USING A SINGLE DISPLAY ENGINE 审中-公开
标题翻译：使用单显示发动机驱动多个显示
公开(公告)号：WO2013089776A2
公开(公告)日：2013-06-20
申请号：PCT/US2011/065491
申请日：2011-12-16
申请人： INTEL CORPORATION , JANUS, Scott , HAYEK, George
发明人： JANUS, Scott , HAYEK, George
IPC分类号： G09G5/36
CPC分类号： G09G3/00 , G06F3/1431 , G09G5/001 , G09G2354/00 , G09G2360/18

4. 发明申请

WO2020190813A1 SYSTEM AND METHODS TO PROVIDE HIERARCHICAL OPEN SECTORING AND VARIABLE SECTOR SIZE FOR CACHE OPERATIONS 审中-公开
公开(公告)号：WO2020190813A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022851
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： APPU, Abhishek , STRIRAMASSARMA, Lakshminarayanan , KOKER, Altug , COLEMAN, Sean , GEORGE, Varghese , HUNTER, JR., Arthur , INSKO, Brent , JANUS, Scott , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , RAY, Joydeep , SINHA, Kamal , SURTI, Prasoonkumar , VAIDYANATHAN, Karthik
IPC分类号： G06F12/12 , G06F12/128 , G06F12/0886 , G06F12/0862 , G06F9/38
摘要： Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

5. 发明申请

WO2020190796A1 SYSTEMS AND METHODS FOR CACHE OPTIMIZATION 审中-公开
公开(公告)号：WO2020190796A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022833
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： KOKER, Altug , RAY, Joydeep , OULD-AHMED-VALL, Elmoustapha , APPU, Abhishek , ANANTARAMAN, Aravindh , ANDREI, Valentin , BILAGI, Durgaprasad , GEORGE, Varghese , INSKO, Brent , JAHAGIRDAR, Sanjeev , JANUS, Scott , K, Pattabhiraman , KIM, SungYe , MAIYURAN, Subramaniam , RANGANATHAN, Vasanth , STRIRAMASSARMA, Lakshminarayanan , TIAN, Xinmin
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/123 , G06F12/126
摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

6. 发明申请

WO2020190429A1 DATA PREFETCHING FOR GRAPHICS DATA PROCESSING 审中-公开
公开(公告)号：WO2020190429A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017897
申请日：2020-02-12
申请人： INTEL CORPORATION , VEMULAPALLI, Vikranth , STRIRAMASSARMA, Lakshminarayanan , MACPHERSON, Mike , ANANTARAMAN, Aravindh , ASHBAUGH, Ben , RAMADOSS, Murali , SADLER, William B. , PEARCE, Jonathan , JANUS, Scott , INSKO, Brent , RANGANATHAN, Vasanth , SINHA, Kamal , HUNTER, Arthur , SURTI, Prasoonkumar , GALOPPO VON BORRIES, Nicolas , RAY, Joydeep , APPU, Abhisek R. , OULD-AHMED-VALL, ElMoustapha , KOKER, Altug , KIM, Sungye , MAIYURAN, Subramaniam , ANDREI, Valentin
发明人： VEMULAPALLI, Vikranth , STRIRAMASSARMA, Lakshminarayanan , MACPHERSON, Mike , ANANTARAMAN, Aravindh , ASHBAUGH, Ben , RAMADOSS, Murali , SADLER, William B. , PEARCE, Jonathan , JANUS, Scott , INSKO, Brent , RANGANATHAN, Vasanth , SINHA, Kamal , HUNTER, Arthur , SURTI, Prasoonkumar , GALOPPO VON BORRIES, Nicolas , RAY, Joydeep , APPU, Abhisek R. , OULD-AHMED-VALL, ElMoustapha , KOKER, Altug , KIM, Sungye , MAIYURAN, Subramaniam , ANDREI, Valentin
IPC分类号： G06F12/0862 , G06F12/0897 , G06F12/0888 , G06F9/38
摘要： Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

7. 发明申请

WO2015048069A1 SECURE VIDEO OUPUT PATH 审中-公开
标题翻译：安全视频OUPUT路径
公开(公告)号：WO2015048069A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/057121
申请日：2014-09-24
申请人： INTEL CORPORATION
发明人： CHHABRA, Siddhartha , SAVAGAONKAR, Uday R. , DEWAN, Prashant , DURHAM, David M. , VEMBU, Balaji , KANG, Xiaozhu , JANUS, Scott , MARTIN, Jason , SCARLATA, Vincent R.
IPC分类号： G06F21/60
CPC分类号： G06F21/82 , G06F21/84 , G06F21/85 , H04N21/4122 , H04N21/4143 , H04N21/4367
摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.
摘要翻译：用于将输出表面位图安全传送到显示引擎的系统和方法。一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述架构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在所述架构受保护的存储器中的指令，建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥具有第二加密密钥的加密密钥。

8. 发明申请

WO2020190810A1 MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS 审中-公开
公开(公告)号：WO2020190810A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022848
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： KOKER, Altug , ASHBAUGH, Ben , JANUS, Scott , ANANTARAMAN, Aravindh , APPU, Abhishek R. , COORAY, Niran , GEORGE, Varghese , HUNTER, Arthur , INSKO, Brent , OULD-AHMED-VALL, ElMoustapha , PANNEER, Selvakumar , RANGANATHAN, Vasanth , RAY, Joydeep , SINHA, Kamal , STRIRAMASSARMA, Lakshminarayanan , SURTI, Prasoonkumar , TANGRI, Saurabh
IPC分类号： G06F12/0804 , G06F12/0893 , G06F15/173
摘要： Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

9. 发明申请

WO2020190799A2 SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION 审中-公开
公开(公告)号：WO2020190799A2
公开(公告)日：2020-09-24
申请号：PCT/US2020/022837
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： KOKER, Altug , RAY, Joydeep , ASHBAUGH, Ben , PEARCE, Jonathan , APPU, Abhishek , RANGANATHAN, Vasanth , STRIRAMASSARMA, Lakshminarayanan , OULD-AHMED-VALL, Elmoustapha , ANANTARAMAN, Aravindh , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , HAREL, Yoav , HUNTER, Arthur Jr. , INSKO, Brent , JANUS, Scott , K, Pattabhiraman , MACPHERSON, Mike , MAIYURAN, Subramaniam , PETRE, Marian Alin , RAMADOSS, Murali , SHAH, Shailesh , SINHA, Kamal , SURTI, Prasoonkumar , VEMULAPALLI, Vikranth
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/02 , G06F12/06 , G06F12/0804 , G06F12/0893 , G06F12/12 , G06F12/128 , G06F15/173 , G06F9/50
摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

10. 发明申请

WO2014084906A1 VIDEO PIPELINE WITH DIRECT LINKAGE BETWEEN DECODING AND POST PROCESSING 审中-公开
标题翻译：在解码和后处理之间具有直接链接的视频管道
公开(公告)号：WO2014084906A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/046322
申请日：2013-06-18
申请人： INTEL CORPORATION , NANDA, Akshat , JANUS, Scott , CHENG, Scott W.
发明人： NANDA, Akshat , JANUS, Scott , CHENG, Scott W.
IPC分类号： H04N7/26
CPC分类号： H04N19/44 , H04N19/42 , H04N19/85
摘要： In general, in one aspect, a decode order for a group of picture (GOP) frame structure for a video stream is modified to include regenerated P frames. The modified decode order includes a regenerated P frame of a P frame decoded prior to a sequence of B frames after last B frame in the sequence of B frames and before next I or P frame. The frames are decoded in modified decode order by a decode engine. The decoded frames are post processed in a display order (only includes regenerated P frames and does not include initial P frames defined in the decode order) by a post processing engine. The post processing engine may ignore the initial P frames or the decode engine may not forward the initial P frames to the post processing engine. The post processed frames may be prepared for presentation by a display engine.
摘要翻译：通常，在一个方面，用于视频流的一组图像（GOP）帧结构的解码顺序被修改为包括再生的P帧。经修改的解码顺序包括在B帧序列中的B帧之后和在下一个I帧或P帧之前的B帧之后的序列之前解码的P帧的再生P帧。帧由解码引擎以修改的解码顺序解码。解码帧以后处理引擎以显示顺序（仅包括再生的P帧，并且不包括以解码顺序定义的初始P帧）进行后处理。后处理引擎可以忽略初始P帧，或者解码引擎可能不将初始P帧转发到后处理引擎。后处理帧可以准备用于由显示引擎呈现。

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