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1. 发明申请

WO2016204782A1 CARBON-BASED INTERFACE FOR EPITAXIALLY GROWN SOURCE/DRAIN TRANSISTOR REGIONS 审中-公开
标题翻译：基于碳的界面，用于外延源源/漏极晶体管区域
公开(公告)号：WO2016204782A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036657
申请日：2015-06-19
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , KEYS, Patrick H. , KENNEL, Harold W. , MEHANDRU, Rishabh , MURTHY, Anand S. , JAMBUNATHAN, Karthik
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L27/0886 , H01L29/0603 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/167 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.
摘要翻译：公开了用于形成在外延生长的S / D区域和沟道区域之间具有一个或多个碳基界面层的p-MOS晶体管的技术。在一些情况下，碳基界面层可以包括碳含量大于20％的碳和0.5-8nm的厚度的单层。在一些情况下，碳基界面层可以包括碳含量小于5％，厚度为2-10nm的单层。在一些这样的情况下，单层还可以包括掺硼的硅（Si：B）或硼掺杂的硅锗（SiGe：B）。在一些情况下，一个或多个另外的界面层可以沉积在碳基界面层上，其中附加界面层包括Si：B和/或SiGe：B。这些技术可用于改善短沟道效应并提高所得晶体管的有效栅极长度。

2. 发明申请

WO2019040071A1 VERTICALLY STACKED FINFETS & SHARED GATE PATTERNING 审中-公开
公开(公告)号：WO2019040071A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/048475
申请日：2017-08-24
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MA, Sean , WEBER, Justin R. , MEHANDRU, Rishabh , CEA, Stephen M. , MORROW, Patrick , KEYS, Patrick H.
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/417
摘要： Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

3. 发明申请

WO2018063407A1 RETROGRADE TRANSISTOR DOPING BY HETEROJUNCTION MATERIALS 审中-公开
标题翻译：退火晶体掺杂异质结材料
公开(公告)号：WO2018063407A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/055034
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： KEYS, Patrick H. , KAM, Hei , MEHANDRU, Rishabh , BUDREVICH, Aaron A.
IPC分类号： H01L29/167 , H01L29/43 , H01L21/8238 , H01L29/49
CPC分类号： H01L27/0924 , H01L21/823892 , H01L27/092 , H01L29/1054 , H01L29/167 , H01L29/43 , H01L29/49 , H01L29/66795 , H01L29/785
摘要： A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.
摘要翻译：一种晶体管，其包括在所述栅极堆叠的相对侧上的栅极堆叠以及源极和漏极; 以及在衬底上的第一材料和第二材料，第一材料设置在衬底和第二材料之间，晶体管的沟道限定在源和漏之间的第二材料中，其中第一材料和第二材料各自包括植入物，并且植入物在第一材料中包括比在第二材料中更大的溶解度。一种形成集成电路结构的方法，包括：在衬底上形成第一材料; 在第一材料上形成第二材料; 将植入物引入到所述第二材料中，其中所述植入物包括在所述第一材料中比在所述第二材料中更大的溶解度; 退火衬底; 以及在衬底上形成晶体管，该晶体管包括含有第二材料的沟道。

4. 发明申请

WO2013095647A1 NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS 审中-公开
标题翻译：具有缠绕接头的纳米结构
公开(公告)号：WO2013095647A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067226
申请日：2011-12-23
申请人： INTEL CORPORATION , CEA, Stephen M. , WEBER, Cory E. , KEYS, Patrick H. , KIM, Seiyon , HAVERTY, Michael G. , SHANKAR, Sadasivan
发明人： CEA, Stephen M. , WEBER, Cory E. , KEYS, Patrick H. , KIM, Seiyon , HAVERTY, Michael G. , SHANKAR, Sadasivan
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/16 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/785 , H01L29/78696
摘要： Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
摘要翻译：描述具有环绕触点的纳米线结构。例如，纳米线半导体器件包括设置在衬底之上的纳米线。沟道区域设置在纳米线中。通道区域具有与长度正交的长度和周长。栅电极堆叠围绕通道区域的整个周边。一对源极和漏极区域设置在沟道区域的任一侧上的纳米线中。源极和漏极区域中的每一个具有与沟道区域的长度正交的周长。第一接触件完全围绕源区域的周边。第二触点完全围绕漏区的周边。

5. 发明申请

WO2018063346A1 METHODS AND APPARATUS TO REMOVE EPITAXIAL DEFECTS IN SEMICONDUCTORS 审中-公开
标题翻译：用于去除半导体中的外延缺陷的方法和设备
公开(公告)号：WO2018063346A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054846
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LILAK, Aaron D. , MEHANDRU, Rishabh , MORROW, Patrick , KEYS, Patrick H.
IPC分类号： H01L21/78 , H01L21/02 , H01L21/768 , H01L21/762 , H01L21/302
CPC分类号： H01L29/785 , H01L21/02 , H01L21/302 , H01L21/304 , H01L21/762 , H01L21/768 , H01L21/76802 , H01L21/78 , H01L29/66 , H01L29/66795
摘要： Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.
摘要翻译：公开了用于去除半导体中的外延缺陷的方法和设备。公开的示例多层管芯结构包括具有第一材料的鳍片，其中鳍片由具有第二材料的第一基板层外延生长，并且鳍片的缺陷部分被蚀刻或抛光。所公开的示例多层管芯结构还包括具有开口的第二衬底层，鳍通过开口延伸。

6. 发明申请

WO2013095384A1 SEMICONDUCTOR DEVICE WITH ISOLATED BODY PORTION 审中-公开
标题翻译：具有隔离体部分的半导体器件
公开(公告)号：WO2013095384A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066171
申请日：2011-12-20
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , CEA, Stephen M. , GHANI, Tahir , GOMEZ, Harry , KAVALIEROS, Jack T. , KEYS, Patrick H. , KIM, Seyiyon , KUHN, Kelin J. , LILAK, Aaron D. , RIOS, Rafael , SAHNI, Mayank
发明人： CAPPELLANI, Annalisa , CEA, Stephen M. , GHANI, Tahir , GOMEZ, Harry , KAVALIEROS, Jack T. , KEYS, Patrick H. , KIM, Seyiyon , KUHN, Kelin J. , LILAK, Aaron D. , RIOS, Rafael , SAHNI, Mayank
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66818 , B82Y10/00 , H01L21/762 , H01L21/76216 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
摘要翻译：描述具有隔离主体部分的半导体器件。例如，半导体结构包括设置在半导体衬底之上的半导体本体。半导体主体包括沟道区和沟道区两侧的一对源极和漏极区。隔离基座设置在半导体本体和半导体衬底之间。栅极电极堆叠至少部分地围绕半导体主体的沟道区域的一部分。

7. 发明申请

WO2018044267A1 QUANTUM DOT DEVICES 审中-公开
标题翻译：量子点设备
公开(公告)号：WO2018044267A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/049368
申请日：2016-08-30
申请人： INTEL CORPORATION
发明人： GEORGE, Hubert C. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , CLARKE, James S. , KEYS, Patrick H.
IPC分类号： H01L29/66 , H01L29/12
CPC分类号： H01L29/82 , B82Y10/00 , H01L29/0673 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66977 , H01L29/7613 , H01L29/7781 , H01L29/7782
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench extending toward the quantum well stack; first and second gates disposed at least partially in the trench; spacers disposed on sides of the first and second gates in the trench, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate; and a third gate disposed at least partially in the trench between the first and second gates and extending between the first and second spacers.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠; 设置在所述量子阱堆叠上方的绝缘材料，其中所述绝缘材料包括朝向所述量子阱堆叠延伸的沟槽; 第一和第二栅极，至少部分地设置在沟槽中; 其中第一间隔物设置在第一栅极的靠近第二栅极的一侧上，并且与第一间隔物物理分离的第二间隔物设置在第一栅极的一侧上第二门的靠近第一门的位置; 以及第三栅极，其至少部分地设置在第一和第二栅极之间的沟槽中并且在第一和第二间隔器之间延伸。

8. 发明申请

WO2017052649A1 DEEP EPI ENABLED BY BACKSIDE REVEAL FOR STRESS ENHANCEMENT & CONTACT 审中-公开
标题翻译：由背压启动的深层EPI应力增强和接触
公开(公告)号：WO2017052649A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052464
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： LILAK, Aaron D. , CEA, Stephen M. , MEHANDRU, Rishabh , MORROW, Patrick , KEYS, Patrick H.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7842 , H01L29/1054 , H01L29/66795 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.
摘要翻译：本发明的实施例包括具有应变通道的非平面晶体管和形成这种晶体管的方法。在一个实施例中，非平面晶体管可以包括半导体衬底。根据实施例，可以在半导体衬底上形成第一源极/漏极（S / D）区域和第二S / D区域，并且通过沟道区域彼此分离。可以在通道区域上形成栅极堆叠。为了增加可能在沟道区域中引起的应变量，实施例可以包括在半导体衬底中形成应变增强开口，从沟道区域下方去除半导体衬底的至少一部分。

9. 发明公开

EP3311417A1 CARBON-BASED INTERFACE FOR EPITAXIALLY GROWN SOURCE/DRAIN TRANSISTOR REGIONS 审中-公开
标题翻译：基于碳的接口用于表面生长源/漏极晶体管区域
公开(公告)号：EP3311417A1
公开(公告)日：2018-04-25
申请号：EP15895823.1
申请日：2015-06-19
申请人： Intel Corporation
发明人： GLASS, Glenn A. , KEYS, Patrick H. , KENNEL, Harold W. , MEHANDRU, Rishabh , MURTHY, Anand S. , JAMBUNATHAN, Karthik
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L27/0886 , H01L29/0603 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/167 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.

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