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1. 发明申请

WO2018182655A1 REMOVAL OF A BOTTOM-MOST NANOWIRE FROM A NANOWIRE DEVICE STACK 审中-公开
公开(公告)号：WO2018182655A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025207
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , KEYS, Patrick , MA, Sean , CEA, Stephen , MEHANDRU, Rishabh
IPC分类号： H01L29/06 , H01L29/41 , H01L21/02 , H01L29/78
摘要： An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

2. 发明申请

WO2017052645A1 METHOD, DEVICE AND SYSTEM TO PROVIDE CAPACITANCE FOR A DYNAMIC RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：用于为动态随机存取存储器提供电容的方法，装置和系统
公开(公告)号：WO2017052645A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052455
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MORROW, Patrick , MEHANDRU, Rishabh , NELSON, Donald W. , CEA, Stephen M.
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/1082 , H01L27/10832 , H01L27/10858 , H01L27/10867
摘要： Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.
摘要翻译：为集成电路的存储单元提供电容的技术和机制。在一个实施例中，存储单元的晶体管包括不同地形成在半导体衬底的第一侧上或其上的结构。在形成晶体管结构的处理之后，进行薄化以使半导体衬底的第二侧，与第一侧相对的第二面露出。随后在半导体衬底中在半导体衬底的暴露的第二侧中或之上进行加工，以在半导体衬底中形成延伸以耦合到晶体管结构之一的电容器。在另一个实施例中，电容器被耦合以基于晶体管的沟道的激活来累积电荷。电容器还被耦合以经由第二侧从存储器单元发送电荷。

3. 发明公开

EP3759738A1 NON-SILICON N-TYPE AND P-TYPE STACKED TRANSISTORS FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：EP3759738A1
公开(公告)日：2021-01-06
申请号：EP18907820.7
申请日：2018-03-02
申请人： INTEL Corporation
发明人： DEWEY, Gilbert , MORROW, Patrick , PILLARISETTY, Ravi , MEHANDRU, Rishabh , HUANG, Cheng-ying , RACHMADY, Willy , LILAK, Aaron
IPC分类号： H01L27/092 , H01L27/098 , H01L21/8252

4. 发明申请

WO2019164494A1 SIDEWALL INTERCONNECT METALLIZATION STRUCTURES FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：WO2019164494A1
公开(公告)日：2019-08-29
申请号：PCT/US2018/019232
申请日：2018-02-22
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , PHAN, Anh , DEWEY, Gilbert , RACHMADY, Willy , MORROW, Patrick
IPC分类号： H01L27/06 , H01L21/768
摘要： Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.

5. 发明申请

WO2019132893A1 INTEGRATED CIRCUITS WITH STACKED TRANSISTORS AND METHODS OF MANUFACTURING THE SAME USING PROCESSES WHICH FABRICATE LOWER GATE STRUCTURES FOLLOWING COMPLETION OF PORTIONS OF AN UPPER TRANSISTOR 审中-公开
公开(公告)号：WO2019132893A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068565
申请日：2017-12-27
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MEHANDRU, Rishabh , DEWEY, Gilbert , RACHMADY, Willy , PHAN, Anh
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
摘要： Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.

6. 发明申请

WO2019040071A1 VERTICALLY STACKED FINFETS & SHARED GATE PATTERNING 审中-公开
公开(公告)号：WO2019040071A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/048475
申请日：2017-08-24
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MA, Sean , WEBER, Justin R. , MEHANDRU, Rishabh , CEA, Stephen M. , MORROW, Patrick , KEYS, Patrick H.
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/417
摘要： Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

7. 发明申请

WO2018063226A1 INVERTED STAIRCASE CONTACT FOR DENSITY IMPROVEMENT TO 3D STACKED DEVICES 审中-公开
标题翻译：反向梯阶接触以改善3D堆叠器件的密度
公开(公告)号：WO2018063226A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054379
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： LILAK, Aaron , MORROW, Patrick , MEHANDRU, Rishabh
IPC分类号： H01L27/115 , H01L21/8234
CPC分类号： H01L27/11582 , H01L21/823475 , H01L27/0688 , H01L27/088 , H01L27/0886 , H01L27/11573 , H01L27/11575
摘要： A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction
摘要翻译：半导体堆叠器件包括通过第一多个介电层彼此分开的第一多个器件层，耦合到第一多个器件层的器件层的接触部分的第一导电通孔，器件层，由第二多个电介质层彼此分开的第二多个器件层以及与第二多个器件层的器件层的接触部分连接的第二电子导电通孔。第一电子导电通孔延伸到半导体堆叠器件的正面，第二导电通孔延伸到半导体堆叠器件的背面。第一多个器件层在第一方向上形成阶梯图案，并且第二多个器件层在从第一方向反转的第二方向上形成阶梯图案

8. 发明申请

WO2017111802A1 INTEGRATED CIRCUIT WITH STACKED TRANSISTOR DEVICES 审中-公开
标题翻译：集成电路与堆叠晶体管器件
公开(公告)号：WO2017111802A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000337
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： MEHANDRU, Rishabh , LILAK, Aaron
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/11582 , H01L28/00
摘要： Embodiments of the present disclosure describe an integrated circuit that may include a first transistor on a first side of a semiconductor substrate and a second transistor on a second side of the semiconductor substrate, wherein the second side is opposite and parallel to the first side. In embodiments, the integrated circuit may further include a first capacitor positioned on the first side of the semiconductor substrate and coupled to the first transistor to form a first memory cell, and a second capacitor positioned on the second side of the semiconductor substrate and coupled to the second transistor to form a second memory cell.
摘要翻译：本公开的实施例描述了一种集成电路，其可以包括在半导体衬底的第一侧上的第一晶体管和在半导体衬底的第二侧上的第二晶体管，其中第二侧是相反的并平行于第一面。在实施例中，集成电路可进一步包括位于半导体衬底的第一侧上并耦合到第一晶体管以形成第一存储器单元的第一电容器，以及位于半导体衬底的第二侧上且耦合到第二晶体管形成第二存储单元。

9. 发明公开

EP3675158A3 THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS 审中-公开
公开(公告)号：EP3675158A3
公开(公告)日：2020-08-05
申请号：EP19209555.2
申请日：2019-11-15
申请人： Intel Corporation
发明人： HUANG, Cheng-Ying , RACHMADY, Willy , DEWEY, Gilbert , LILAK, Aaron , JUN, Kimin , MUELLER, Brennen , MANNEBACH, Ehren , PHAN, Anh , MORROW, Patrick , YOO, Hui Jae , KAVALIEROS, Jack
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/092
摘要： Embodiments herein describe techniques for a semiconductor device including a first transistor (120) stacked above and self-aligned with a second transistor (110), where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode (129), a first channel layer (123) including a first channel material and separated from the first gate electrode by a first gate dielectric layer (128), and a first source electrode (125) coupled to the first channel layer. The second transistor includes a second gate electrode (109), a second channel layer (103) including a second channel material and separated from the second gate electrode by a second gate dielectric layer (108), and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer (115). Other embodiments may be described and/or claimed.

10. 发明公开

EP3678171A1 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP OXIDATION APPROACH 审中-公开
公开(公告)号：EP3678171A1
公开(公告)日：2020-07-08
申请号：EP19208909.2
申请日：2019-11-13
申请人： Intel Corporation
发明人： RACHMADY, Willy , DEWEY, Gilbert , KAVALIEROS, Jack , LILAK, Aaron , MORROW, Patrick , PHAN, Anh , HUANG, Cheng-Ying , MANNEBACH, Ehren
IPC分类号： H01L21/8234 , H01L29/06 , H01L29/66 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/092
摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires (304C, 304D, 314A-314D) above one or more oxidized nanowires (350A, 230B). A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

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