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1. 发明申请

WO2018182693A1 TEMPLATE GROWTH SURFACE FOR FIN FIELD EFFECT TRANSISTORS (FINFETs) 审中-公开
公开(公告)号：WO2018182693A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025410
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , GARDNER, Sanaz, K. , METZ, Matthew, V. , DEWEY, Gilbert , HUANG, Cheng-Ying , MA, Sean, T. , MINUTILLO, Nicholas, G. , MURTHY, Anand, S. , KAVALIEROS, Jack, T. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L29/66 , H01L21/02 , H01L29/04
摘要： In various embodiments, the disclosure describes a fin field effect transistor (FinFET) device having a template growth surface for the growth of the channel and/or fin of the FinFET. In one embodiment, the template growth surface can include a predetermined facet or surface of a semiconductor material. For example, for the case of a semiconductor material comprising gallium arsenide, a facet having Miller indices of (111) can serve as the second template growth surface. In one embodiment, for the case of a semiconductor material comprising gallium arsenide, a second semiconductor material comprising the fin and/or channel of the FinFET can be an indium gallium arsenide (InGaAs) material.

2. 发明申请

WO2017111873A1 A METHOD TO ACHIEVE A UNIFORM GROUP IV MATERIAL LAYER IN AN ASPECT RATIO TRAPPING TRENCH 审中-公开
标题翻译：在高差俘获孔径中实现均匀IV族材料层的方法
公开(公告)号：WO2017111873A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000503
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz, K. , RACHMADY, Willy , LE, Van, H. , METZ, Matthew, V. , KIM, Seiyon , AGRAWAL, Ashish , KAVALIEROS, Jack, T.
IPC分类号： H01L21/334 , H01L21/335 , H01L29/78
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795
摘要： Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.
摘要翻译：本公开的相关领域属于晶体管器件领域，并且具体地涉及使用纵横比俘获沟槽（ART）工艺技术形成的FinFET器件结构。例如，与本公开一致的FinFET器件包括第一鳍状结构，该第一鳍状结构包括第一下翅片部分顶上的第一上翅片部分和包括第二下翅片部分顶上的第二上翅片部分的第二翅片结构。第一和第二上鳍结构包括第IV族材料，第一和第二下鳍结构包括III-V族材料。

3. 发明申请

WO2017111848A8 TRANSISTOR INCLUDING TENSILE-STRAINED GERMANIUM CHANNEL 审中-公开
标题翻译：晶体管包括拉伸应变的锗通道
公开(公告)号：WO2017111848A8
公开(公告)日：2017-06-29
申请号：PCT/US2015/000414
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra, S. , GLASS, Glenn, A. , MURTHY, Anand, S. , JAMBUNATHAN, Karthik , RACHMADY, Willy , DEWEY, Gilbert , GHANI, Tahir , KAVALIEROS, Jack, T.
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p- type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n- MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).
摘要翻译：公开了用于形成包括拉伸应变锗（Ge）沟道材料的晶体管结构的技术。晶体管结构可用于n型和p型晶体管器件中的任一个或两者，因为拉伸应变的Ge具有适用于这两种类型的非常高的载流子迁移率特性。因此，可以通过使用本文描述的技术形成CMOS器件中包括的n-MOS和p-MOS器件来实现简化的CMOS集成方案。在一些情况下，拉伸应变Ge可以通过在晶格常数高于Ge的III-V族材料上外延生长Ge材料和/或通过对模具施加宏观3点弯曲来实现在其上形成晶体管。该技术可以用于形成具有平面或非平面配置的晶体管，诸如翅片配置（例如，finFET或三栅极）或全栅（GAA）配置（包括至少一个纳米线）。

4. 发明申请

WO2017111797A1 FABRICATION OF NON-PLANAR IGZO DEVICES FOR IMPROVED ELECTROSTATICS 审中-公开
标题翻译：非平面IGZO装置的制造以改进静电学
公开(公告)号：WO2017111797A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000319
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： LE, Van, H. , DEWEY, Gilbert , RIOS, Rafael , KAVALIEROS, Jack, T. , RADOSAVLJEVIC, Marko , MILLARD, Kent, E. , FRENCH, Marc, C. , AGRAWAL, Ashish , CHU-KUNG, Benjamin , ARCH, Ryan, E.
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L27/12 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78
摘要： Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
摘要翻译：本发明的实施例包括非平面InGaZnO（IGZO）晶体管和形成这种器件的方法。在一个实施例中，IGZO晶体管可以包括衬底以及形成在衬底上的源极区和漏极区。根据一个实施例，IGZO层可以形成在衬底上方并且可以电耦合到源极区域和漏极区域。其他实施例包括通过栅极电介质与IGZO层分离的栅电极。在一个实施例中，栅极电介质接触IGZO层的多于一个表面。在一个实施例中，IGZO晶体管是finfet晶体管。在另一个实施例中，IGZO晶体管是纳米线或纳米带晶体管。本发明的实施例还可以包括形成在集成电路芯片的线堆栈（BEOL）的后端的非平面IGZO晶体管。

5. 发明公开

EP2517251A2 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 审中-公开
标题翻译：法形成的量子BAY TRANSISTORS联系
公开(公告)号：EP2517251A2
公开(公告)日：2012-10-31
申请号：EP10843440.8
申请日：2010-12-02
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , KAVALIEROS, Jack, T. , CHU-KUNG, Benjamin , RACHMADY, Willy , HUDAIT, Mantu, K. , MUKHERJEE, Niloy , RADOSAVLJEVIC, Marko , CHAU, Robert, S.
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

6. 发明申请

WO2018182714A1 TOP-GATED THIN FILM TRANSISTORS WITH MULTIPLE CHANNEL LAYERS 审中-公开
公开(公告)号：WO2018182714A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025503
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek, A. , LE, Van H. , DEWEY, Gilbert , GHANI, Tahir , KAVALIEROS, Jack, T.
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/66742 , H01L21/8258 , H01L27/0688 , H01L27/088 , H01L29/66 , H01L29/786 , H01L29/78609
摘要： Embodiments herein describe techniques for a semiconductor device including a top-gated TFT having high mobility, while keeping the leakage low. Embodiments may include a dielectric layer above a substrate and multiple channel layers above the dielectric layer. For example, a first channel layer including a first material may be above the dielectric layer, and a second channel layer including a second material may be above the first channel layer, wherein the first material may have a lower leakage than the second material, and the second material may have a higher mobility than the first material. Embodiments may further include a source electrode, a drain electrode, and a gate electrode above the second channel layer. Other embodiments may be described and/or claimed.

7. 发明申请

WO2017155540A1 TECHNIQUES FOR FORMING TRANSISTORS INCLUDING GROUP III-V MATERIAL NANOWIRES USING SACRIFICIAL GROUP IV MATERIAL LAYERS 审中-公开
标题翻译：使用牺牲性第IV族材料层形成晶体管的技术，包括III-V族材料纳米线
公开(公告)号：WO2017155540A1
公开(公告)日：2017-09-14
申请号：PCT/US2016/021952
申请日：2016-03-11
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra, S. , GLASS, Glenn, A. , MURTHY, Anand, S. , JAMBUNATHAN, Karthik , RACHMADY, Willy , DEWEY, Gilbert , GHANI, Tahir , KAVALIEROS, Jack, T.
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.
摘要翻译：公开了使用牺牲IV族半导体材料层来形成包括一个或多个III-V族半导体材料纳米线的晶体管的技术。在一些情况下，晶体管可以包括全栅（GAA）配置。在一些情况下，所述技术可以包括形成替代鳍堆叠，所述替代鳍堆叠包括形成在IV族材料缓冲层（诸如硅，锗，锗等）上的III-V族材料层（诸如砷化铟镓，砷化铟或锑化铟）或硅锗），使得随后可以使用选择性蚀刻工艺去除组IV-V缓冲层，以使III-V族材料在晶体管沟道中用作纳米线。在一些这样的情况下，III-V族材料层可以假性生长至下面的IV族材料，从而不形成错配位错。这些技术可用于形成包括任何数量纳米线的晶体管。

8. 发明申请

WO2015147858A1 SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES 审中-公开
标题翻译：选择性外形III-V材料的设备
公开(公告)号：WO2015147858A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032149
申请日：2014-03-28
申请人： INTEL CORPORATION
发明人： METZ, Matthew, V. , KAVALIEROS, Jack, T. , DEWEY, Gilbert , RACHMADY, Willy , CHU-KUNG, Benjamin , RADOSAVLJEVIC, Marko , THEN, Han Wui , PILLARISETTY, Ravi , CHAU, Robert, S.
IPC分类号： H01L21/20 , H01L21/18
CPC分类号： H01L29/205 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02502 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/76224 , H01L21/823431 , H01L29/1054 , H01L29/66522 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/7851
摘要： An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.
摘要翻译：实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。本文还包括其它实施例。

9. 发明申请

WO2011087606A2 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 审中-公开
标题翻译：形成量子阱晶体管的技术
公开(公告)号：WO2011087606A2
公开(公告)日：2011-07-21
申请号：PCT/US2010/058683
申请日：2010-12-02
申请人： INTEL CORPORATION , PILLARISETTY, Ravi , KAVALIEROS, Jack, T. , CHU-KUNG, Benjamin , RACHMADY, Willy , HUDAIT, Mantu, K. , MUKHERJEE, Niloy , RADOSAVLJEVIC, Marko , CHAU, Robert, S.
发明人： PILLARISETTY, Ravi , KAVALIEROS, Jack, T. , CHU-KUNG, Benjamin , RACHMADY, Willy , HUDAIT, Mantu, K. , MUKHERJEE, Niloy , RADOSAVLJEVIC, Marko , CHAU, Robert, S.
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

10. 发明申请

WO2007064492A1 DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE 审中-公开
标题翻译： III-V族半导体器件的介电接口
公开(公告)号：WO2007064492A1
公开(公告)日：2007-06-07
申请号：PCT/US2006/044601
申请日：2006-11-17
申请人： INTEL CORPORATION , BRASK, Justin, K. , DATTA, Suman , DOCZY, Mark, L. , BLACKWELL, James, M. , METZ, Matthew, V. , KAVALIEROS, Jack, T. , CHAU, Robert, S.
发明人： BRASK, Justin, K. , DATTA, Suman , DOCZY, Mark, L. , BLACKWELL, James, M. , METZ, Matthew, V. , KAVALIEROS, Jack, T. , CHAU, Robert, S.
IPC分类号： H01L21/314 , H01L29/51 , H01L21/28
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

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