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1. 发明申请

WO2019190508A1 III-V SOURCE/DRAIN IN TOP NMOS TRANSISTORS FOR LOW TEMPERATURE STACKED TRANSISTOR CONTACTS 审中-公开
公开(公告)号：WO2019190508A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/024936
申请日：2018-03-28
申请人： INTEL CORPORATION , DEWEY, Gilbert , PILLARISETTY, Ravi , SHARMA, Abhishek A. , LILAK, Aaron D. , RACHMADY, Willy , MEHANDRU, Rishabh , JUN, Kimin , PHAN, Anh , YOO, Hui Jae , MORROW, Patrick , HUANG, Cheng-Ying
发明人： DEWEY, Gilbert , PILLARISETTY, Ravi , SHARMA, Abhishek A. , LILAK, Aaron D. , RACHMADY, Willy , MEHANDRU, Rishabh , JUN, Kimin , PHAN, Anh , YOO, Hui Jae , MORROW, Patrick , HUANG, Cheng-Ying
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

2. 发明申请

WO2019190505A1 STACKED TRANSISTORS WITH SI PMOS AND HIGH MOBILITY THIN FILM TRANSISTOR NMOS 审中-公开
公开(公告)号：WO2019190505A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/024914
申请日：2018-03-28
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , PILLARISETTY, Ravi , SHARMA, Abhishek A. , LILAK, Aaron D. , RACHMADY, Willy , MEHANDRU, Rishabh , JUN, Kimin , PHAN, Anh , YOO, Hui Jae , MORROW, Patrick , HUANG, Cheng-Ying
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/786 , H01L29/49
摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).

3. 发明申请

WO2019168521A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2019168521A1
公开(公告)日：2019-09-06
申请号：PCT/US2018/020195
申请日：2018-02-28
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , KAVALIEROS, Jack , YOUNG, Ian , METZ, Matthew , RACHMADY, Willy , AVCI, Uygar , AGRAWAL, Ashish , CHU-KUNG, Benjamin
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/423 , H01L29/417 , H01L21/8234 , H01L21/28
摘要： Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of later TFETs. In an embodiment, the disclosed vertical TFETs can have a drain that is deposited in a trench.

4. 发明申请

WO2019143340A9 VERTICAL DIODE IN STACKED TRANSISTOR ARCHITECTURE 审中-公开
公开(公告)号：WO2019143340A9
公开(公告)日：2019-07-25
申请号：PCT/US2018/014267
申请日：2018-01-18
申请人： INTEL CORPORATION
发明人： LILAK, Aaron D. , MORROW, Patrick , PHAN, Anh , HUANG, Cheng-Ying , MEHANDRU, Rishabh , DEWEY, Gilbert , RACHMADY, Willy
IPC分类号： H01L27/08 , H01L29/78 , H01L29/66 , H01L29/861 , H01L21/8234 , H01L27/092
摘要： An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

5. 发明申请

WO2019125501A1 QUANTUM DOT DEVICES 审中-公开
公开(公告)号：WO2019125501A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/068371
申请日：2017-12-23
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , RACHMADY, Willy , SINGH, Kanwaljit , THOMAS, Nicole K. , GEORGE, Hubert C. , YOSCOVITS, Zachary R. , CAUDILLO, Roman , AMIN, Payam , ROBERTS, Jeanette M. , CLARKE, James S.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12
CPC分类号： H01L29/82 , H01L29/12 , H01L29/7782 , H01L29/7786
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

6. 发明申请

WO2019035842A1 TUNNELING FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2019035842A1
公开(公告)日：2019-02-21
申请号：PCT/US2017/047523
申请日：2017-08-18
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , RACHMADY, Willy , METZ, Matthew V. , AGRAWAL, Ashish , CHU-KUNG, Benjamin , AVCI, Uygar E. , KAVALIEROS, Jack T. , YOUNG, Ian A.
IPC分类号： H01L29/739 , H01L29/73 , H01L29/772
摘要： Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

7. 发明申请

WO2018063403A1 ART TRENCH SPACERS TO ENABLE FIN RELEASE FOR NON-LATTICE MATCHED CHANNELS 审中-公开
标题翻译： ART TRENCH SPACERS使非FINAL RELEASE适用于无格式匹配的通道
公开(公告)号：WO2018063403A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/055028
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , METZ, Matthew V. , MA, Sean T. , HUANG, Cheng-Ying , GHANI, Tahir , MURTHY, Anand S. , KENNEL, Harold W. , MINUTILLO, Nicholas G. , KAVALIEROS, Jack T. , RACHMADY, Willy
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8234
摘要： A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.
摘要翻译：一种晶体管器件，包括设置在源极和漏极之间的衬底上的沟道，设置在所述沟道上的栅电极，其中所述沟道包括沟道材料，所述沟道材料与相同材料的本体分离在衬底上。一种方法，包括在集成电路衬底上的电介质层中形成沟槽，所述沟槽包括用于包括宽度的晶体管主体的尺寸; 在沟槽的一部分中沉积间隔层，间隔层使沟槽的宽度变窄; 穿过间隔层在沟槽中形成沟道材料; 使所述介电层凹陷以限定所述沟道材料的第一部分和所述沟道材料的第二部分; 以及将沟道材料的第一部分与沟道材料的第二部分分开。

8. 发明申请

WO2018063372A1 SUPPERLATICE CHANNEL INCLUDED IN A TRENCH 审中-公开
标题翻译：包含在道具中的支援渠道
公开(公告)号：WO2018063372A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054911
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , METZ, Matthew V. , RACHMADY, Willy , DEWEY, Gilbert , KAVALIEROS, Jack T.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423
摘要： An embodiment includes an apparatus comprising: a trench included in an insulation layer that is formed on a substrate, the trench having a top portion and a bottom portion between the top portion and the substrate; a first layer which comprises a first material and is included in the bottom portion; and a superlattice, in the trench and on the first layer, including second and third layers that directly contact each other; wherein: (a) the second and third layers respectively include second and third materials, (b) the second and third materials have different chemical compositions from each other, and (c) the first layer is thicker than each of the second and third. Other embodiments are described herein.
摘要翻译：一种实施方式包括一种装置，该装置包括：包括在形成在基板上的绝缘层中的沟槽，所述沟槽具有位于所述顶部和所述基板之间的顶部和底部; 包含第一材料并包含在底部中的第一层; 和超晶格，在沟槽中和第一层上，包括彼此直接接触的第二层和第三层; 其中：（a）第二和第三层分别包括第二和第三材料，（b）第二和第三材料彼此具有不同的化学组成，并且（c）第一层比第二和第三层中的每一个都厚。这里描述了其他实施例。

9. 发明申请

WO2018063290A1 STIFF QUANTUM LAYERS TO SLOW AND OR STOP DEFECT PROPAGATION 审中-公开
标题翻译：强化量子层缓慢或停止缺陷传播
公开(公告)号：WO2018063290A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054676
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： METZ, Matthew , DEWEY, Gilbert , KENNEL, Harold W. , HUANG, Cheng-Ying , MA, Sean T. , RACHMADY, Willy
IPC分类号： H01L29/12 , H01L21/02 , H01L21/20
CPC分类号： H01L29/122 , H01L21/02543 , H01L21/02546 , H01L29/20
摘要： Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.
摘要翻译：这里公开了半导体器件，计算设备和相关方法。一种半导体器件包括种子材料，与种子材料接触的外延材料以及包括大于外延材料的弹性刚度的弹性刚度的至少一个量子区域。外延材料具有与晶种材料的晶格参数相差至少阈值量的晶格参数。量子区域的晶格参数在外延材料的晶格参数的阈值量内。一种方法包括在种子材料上设置外延材料，在外延材料上设置量子区域，并在该量子区域上设置外延材料。

10. 发明申请

WO2018057043A1 SOURCE/DRAIN RECESS ETCH STOP LAYERS AND BOTTOM WIDE-GAP CAP FOR III-V MOSFETS 审中-公开
标题翻译： SOURCE /漏极钳位停止层和III-V MOSFET的宽侧隙盖
公开(公告)号：WO2018057043A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053831
申请日：2016-09-26
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MA, Sean T. , KENNEL, Harold
IPC分类号： H01L29/78 , H01L29/778 , H01L29/06 , H01L21/768
摘要： A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.
摘要翻译：缓冲层沉积在衬底上。第一III-V族半导体层沉积在缓冲层上。在第一III-V半导体层上沉积第二III-V族半导体层。第二III-V族半导体层包括沟道部分和源极/漏极部分。第一III-V半导体层用作蚀刻停止层以蚀刻第二III-V族半导体层的一部分以形成源极/漏极部分。

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