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1. 发明申请

WO2019066813A1 METHOD, DEVICE AND SYSTEM FOR PROVIDING ETCHED METALLIZATION STRUCTURES 审中-公开
公开(公告)号：WO2019066813A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053786
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： ECTON, Jeremy , HAEHN, Nicholas , OJEDA, Oscar , ROY, Arnab , WHITE, Timothy , NAD, Suddhasattwa , WANG, Hsin-Wei
IPC分类号： H01L21/768 , H01L21/306
摘要： Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

2. 发明公开

EP4163965A2 SEMICONDUCTOR DEVICE WITH TALL AND SLENDER INTERCONNECTING BUMPS AND CORRESPONDING MANUFACTURING METHOD 审中-实审
公开(公告)号：EP4163965A2
公开(公告)日：2023-04-12
申请号：EP22189545.1
申请日：2022-08-09
申请人： INTEL Corporation
发明人： OZCAN, Onur , CETEGEN, Edvin , CHO, Steve , HAEHN, Nicholas , VEHONSKY, Jacob , DUAN, Gang
IPC分类号： H01L23/485 , H01L21/603
摘要： A semiconductor device (100) includes a first plate-like element (104) having a first substantially planar connection surface (112) with a first connection pad (114) and a second plate-like element (102) having a second substantially planar connection surface (110) with a second connection pad (114) corresponding to the first connection pad (114); and a connection (106+108) electrically and physically coupling the first and second plate-like elements (104, 102) and arranged between the first and second connection pads (114). The connection (106+108) includes an elongate element (108) arranged on the first connection pad (114) and extending toward the second connection pad (114) and solder (106) in contact with the second connection pad (114) and the elongate element (108). The first or second plate-like element (104, 102) may comprise a die, in particular, a bridge die. An electronic system (800) may comprise the semiconductor device (100) and an electrical component electrically coupled to the first plate-like element, wherein the electrical component may comprise an antenna (878), a touch screen and/or a personal computer. A method of assembling a semiconductor device (100) comprises: heating first and second plate-like elements (104, 102) to a solder reflow temperature; and pressing the first plate-like element (104) against the second plate-like element (102) with pressing an elongate element (109) extending from a first connection pad (114) on the first plate-like element (104) toward a second connection pad (114) on the second plate-like element (102). The resulting connection formation (e.g., between a solder bump (107) on the second connection pad (114) and a corresponding elongate element (109)) may depend on the location of the connection and the deformations, warping, or other factors that affect the space between the first and second plate-like elements (104, 102) at various locations. A preassembled height (122) of the elongate element (109) may comprise a pillar (128) and the pressing may comprise pressing the first plate-like element (104) until the elongate element (109) contacts the second connection pad (114) and continuing to press until a selected compression limit is reached. A preassembled height (122) of the elongate element (109) may comprise a pillar (128) (e.g., a hard pillar or a malleable pillar) and a solder cap (126), the pressing step forcing the solder cap (126) to reflow, in particular, to reflow with a solder bump (107) on the second connection pad (114). Alternatively, the elongate element (109) may comprise deformation signs (130), wherein the solder may comprise a first solder material and the elongate element (109) may comprise a second solder material having a melting point higher than the first solder material, resulting in a malleable pillar.

3. 发明公开

EP4163965A3 SEMICONDUCTOR DEVICE WITH TALL AND SLENDER INTERCONNECTING BUMPS AND CORRESPONDING MANUFACTURING METHOD 审中-实审
公开(公告)号：EP4163965A3
公开(公告)日：2023-07-19
申请号：EP22189545.1
申请日：2022-08-09
申请人： INTEL Corporation
发明人： OZCAN, Onur , CETEGEN, Edvin , CHO, Steve , HAEHN, Nicholas , VEHONSKY, Jacob , DUAN, Gang
IPC分类号： H01L23/485 , H01L21/603
摘要： A semiconductor device (100) includes a first plate-like element (104) having a first substantially planar connection surface (112) with a first connection pad (114) and a second plate-like element (102) having a second substantially planar connection surface (110) with a second connection pad (114) corresponding to the first connection pad (114); and a connection (106+108) electrically and physically coupling the first and second plate-like elements (104, 102) and arranged between the first and second connection pads (114). The connection (106+108) includes an elongate element (108) arranged on the first connection pad (114) and extending toward the second connection pad (114) and solder (106) in contact with the second connection pad (114) and the elongate element (108). The first or second plate-like element (104, 102) may comprise a die, in particular, a bridge die. An electronic system (800) may comprise the semiconductor device (100) and an electrical component electrically coupled to the first plate-like element, wherein the electrical component may comprise an antenna (878), a touch screen and/or a personal computer. A method of assembling a semiconductor device (100) comprises: heating first and second plate-like elements (104, 102) to a solder reflow temperature; and pressing the first plate-like element (104) against the second plate-like element (102) with pressing an elongate element (109) extending from a first connection pad (114) on the first plate-like element (104) toward a second connection pad (114) on the second plate-like element (102). The resulting connection formation (e.g., between a solder bump (107) on the second connection pad (114) and a corresponding elongate element (109)) may depend on the location of the connection and the deformations, warping, or other factors that affect the space between the first and second plate-like elements (104, 102) at various locations. A preassembled height (122) of the elongate element (109) may comprise a pillar (128) and the pressing may comprise pressing the first plate-like element (104) until the elongate element (109) contacts the second connection pad (114) and continuing to press until a selected compression limit is reached. A preassembled height (122) of the elongate element (109) may comprise a pillar (128) (e.g., a hard pillar or a malleable pillar) and a solder cap (126), the pressing step forcing the solder cap (126) to reflow, in particular, to reflow with a solder bump (107) on the second connection pad (114). Alternatively, the elongate element (109) may comprise deformation signs (130), wherein the solder may comprise a first solder material and the elongate element (109) may comprise a second solder material having a melting point higher than the first solder material, resulting in a malleable pillar.

4. 发明公开

EP4156254A1 ELECTRONIC PACKAGING ARCHITECTURE WITH CUSTOMIZED VARIABLE METAL THICKNESS ON SAME BUILDUP LAYER 审中-实审
公开(公告)号：EP4156254A1
公开(公告)日：2023-03-29
申请号：EP22183759.4
申请日：2022-07-08
申请人： Intel Corporation
发明人： ECTON, Jeremy , DARMAWIKARTA, Kristof , NAD, Suddhasattwa , OJEDA, Oscar , NIE, Bai , MARIN, Brandon , DUAN, Gang , VEHONSKY, Jacob , OZKAN, Onur , HAEHN, Nicholas
IPC分类号： H01L23/498 , H01L23/538 , H01L21/48
摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

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