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1. 发明申请

WO2018182610A1 PACKAGE ARCHITECTURE UTILIZING PHOTOIMAGEABLE DIELECTRIC (PID) FOR REDUCED BUMP PITCH 审中-公开
公开(公告)号：WO2018182610A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024995
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： MAY, Robert A. , BOYAPATI, Sri Ranga Sai , DARMAWIKARTA, Kristof , TANAKA, Hiroki , PIETAMBARAM, Srinivas V. , TRUONG, Frank , AKKINEPALLY, Praneeth , BROWN, Andrew J. , LINK, Lauren A. , CHATTERJEE, Prithwish
IPC分类号： H01L21/56 , H01L23/498 , H01L23/00
摘要： An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

2. 发明申请

WO2018044326A1 AN APPARATUS WITH EMBEDDED FINE LINE SPACE IN A CAVITY, AND A METHOD FOR FORMING THE SAME 审中-公开
标题翻译：具有嵌入腔中的精细线空间的设备以及形成该腔的方法
公开(公告)号：WO2018044326A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/050268
申请日：2016-09-02
申请人： INTEL CORPORATION
发明人： DARMAWIKARTA, Kristof , MAY, Robert A. , DENG, Yikang , PARK, Ji Yong , MOUSSALLEM, Maroun D. , ALUR, Amruthavalli P. , BOYAPATI, Sri Ranga Sai , MAY, Lilia
IPC分类号： H05K3/46 , H05K3/34 , H05K1/18 , H05K3/18
CPC分类号： H05K3/4697 , H01L23/13 , H01L23/5389 , H01L24/20 , H01L2224/04105 , H01L2224/16227 , H01L2224/73259 , H01L2224/92224 , H01L2924/15153 , H01L2924/15192 , H01L2924/15313 , H05K1/183 , H05K3/4682 , H05K3/4688 , H05K2203/308
摘要： An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.
摘要翻译：提供了一种设备，其包括：在印刷电路板（PCB）的基板中制造的空腔; 嵌入该空腔中的多个焊球; 以及在所述衬底内的水平迹线，其中所述水平迹线部分地直接在所述多个焊球之下并且被耦合到所述多个焊球以及所述衬底中的另一个迹线或通孔，使得所述多个焊球之下的衬底区域是独立于空腔下的停止层。

3. 发明申请

WO2017171787A1 METHODS OF PROMOTING ADHESION BETWEEN DIELECTRIC AND CONDUCTIVE MATERIALS IN PACKAGING STRUCTURES 审中-公开
标题翻译：促进包装结构中介电材料与导电材料之间粘合的方法
公开(公告)号：WO2017171787A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025216
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： MAY, Robert A. , CHEN, Chi-Mon , DARMAWIKARTA, Kristof , PARK, Ji Yong , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L23/485 , H01L23/525
CPC分类号： H01L23/485 , H01L23/49894 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2224/13101 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/00014 , H01L2924/014 , H01L2924/0665 , H01L2924/00
摘要： Methods of improving adhesion between dielectric and metallic materials in package substrates are described. Those methods/structures may include providing a package substrate comprising a conductive interconnect structure, forming an alloy on the conductive interconnect structure; and forming a dielectric build up material on the conductive interconnect structure, wherein the dielectric buildup material comprises a siloxane based adhesion promoter throughout the buildup material, and wherein the siloxane based adhesion promoter forms a covalent bond with the alloy.
摘要翻译：描述了改善封装衬底中的电介质和金属材料之间的粘合性的方法。那些方法/结构可以包括提供包括导电互连结构的封装衬底，在导电互连结构上形成合金; 以及在所述导电互连结构上形成电介质堆积材料，其中所述电介质堆积材料包括贯穿所述堆积材料的基于硅氧烷的助粘剂，并且其中所述基于硅氧烷的助粘剂与所述合金形成共价键。

4. 发明申请

WO2017105388A1 SUBSTRATE INTEGRATED WAVEGUIDE 审中-公开
标题翻译：基片集成波导
公开(公告)号：WO2017105388A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/065511
申请日：2015-12-14
申请人： INTEL CORPORATION
发明人： MAY, Robert Alan , DARMAWIKARTA, Kristof , JAIN, Rahul , BOYAPATI, Sri Ranga Sai , MOUSSALLEM, Maroun , MANEPALLI, Rahul N. , PIETAMBARAM, Srinivas
IPC分类号： G02B6/132
CPC分类号： G02B6/122 , G02B6/132 , G02B6/134
摘要： This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.
摘要翻译：该文献尤其讨论了一种波导，该波导包括第一金属和第二金属，该第一金属具有接近介电材料的外表面和限定波导的路径的内表面，在该接收器处接收光信号的方法所述波导的内表面并且沿着所述波导的所述路径的至少一部分传输所述光信号。一种将波导集成在衬底中的方法包括在载体衬底的第一表面上沉积牺牲金属以形成波导的核心，在牺牲金属上沉积第一金属以及载体衬底的第一表面的至少一部分，形成波导的外表面和与牺牲金属分开的导体，并且在载体衬底的第一表面上围绕导体沉积介电材料。

5. 发明申请

WO2022245433A1 INTEGRATED CIRCUIT PACKAGE INTERPOSERS WITH PHOTONIC & ELECTRICAL ROUTING 审中-公开
公开(公告)号：WO2022245433A1
公开(公告)日：2022-11-24
申请号：PCT/US2022/022659
申请日：2022-03-30
申请人： INTEL CORPORATION
发明人： DUONG, Benjamin , GAAN, Sandeep , PIETAMBARAM, Srinivas , LI, Wenchao , DARMAWIKARTA, Kristof , AGRAWAL, Ankur , MAHAJAN, Ravindranath
IPC分类号： H01L23/00 , H01L25/18 , H01L25/065
摘要： IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350°C, or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.

6. 发明申请

WO2018208317A1 DIELECTRIC FOR HIGH DENSITY SUBSTRATE INTERCONNECTS 审中-公开
公开(公告)号：WO2018208317A1
公开(公告)日：2018-11-15
申请号：PCT/US2017/032436
申请日：2017-05-12
申请人： INTEL CORPORATION
发明人： MAY, Robert A. , BROWN, Andrew J. , BOYAPATI, Sri Ranga Sai , DARMAWIKARTA, Kristof
IPC分类号： H01L21/762 , H01L21/02 , C08K5/357 , C08K5/372 , C08K3/38 , C08K3/22 , C08K5/548 , C08K5/55 , C08K3/08
摘要： The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ≥100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.

7. 发明申请

WO2017160459A1 PLASMA ETCHING OF SOLDER RESIST OPENINGS 审中-公开
标题翻译：等离子刻蚀抗焊剂开口
公开(公告)号：WO2017160459A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018195
申请日：2017-02-16
申请人： INTEL CORPORATION
发明人： DARMAWIKARTA, Kristof , JAIN, Rahul , MAY, Robert Alan , LI, Sheng , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/3213 , H01L21/225
CPC分类号： H05K3/0041 , H05K1/0313 , H05K1/09 , H05K3/0055 , H05K3/3452 , H05K2203/0502 , H05K2203/0548 , H05K2203/0562 , H05K2203/0588 , H05K2203/095
摘要： A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.
摘要翻译：
一种形成电子组件的方法。该方法包括用阻焊剂覆盖介电层上的图案化导电层; 在所述阻焊剂上沉积金属层; 在所述金属层上沉积光刻胶; 构图光刻胶; 蚀刻从光致抗蚀剂暴露的金属层以形成金属掩模; 去除光刻胶; 并等离子蚀刻从金属掩模暴露的阻焊层。用于电子卡安全保护的电子组件。该电子组件包括位于电介质层上的图案化导电层; 以及覆盖图案化导电层和介电层的阻焊剂，其中阻焊剂包括暴露图案化导电层的开口，其中阻焊剂中的开口仅在各个开口的侧壁上具有有机材料。

8. 发明公开

EP3716320A1 INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES 审中-公开
公开(公告)号：EP3716320A1
公开(公告)日：2020-09-30
申请号：EP20156743.5
申请日：2020-02-11
申请人： INTEL Corporation
发明人： PIETAMBARAM, Srinivas V. , IBRAHIM, Tarek , DARMAWIKARTA, Kristof , MANEPALLI, Rahul N. , MALLIK, Debendra , SANKMAN, Robert L
IPC分类号： H01L23/15 , H01L23/538
摘要： A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

9. 发明申请

WO2023048813A1 GLASS SUBSTRATE EMBEDDED PIC TO PIC AND OFF-CHIP PHOTONIC COMMUNICATIONS 审中-公开
公开(公告)号：WO2023048813A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/038217
申请日：2022-07-25
申请人： INTEL CORPORATION
发明人： DUONG, Benjamin , DARMAWIKARTA, Kristof , PIETAMBARAM, Srinivas, V. , GRUJICIC, Darko , NIE, Bai , IBRAHIM, Tarek, A. , AGRAWAL, Ankur , GAAN, Sandeep , MAHAJAN, Ravindranath, V. , ALEKSOV, Aleksandar
IPC分类号： H01L25/16 , H01L25/065 , G02B6/124 , G02B6/43 , G02B6/42 , H01L25/00 , G02B6/12
摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

10. 发明申请

WO2022186937A1 CORELESS ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS 审中-公开
公开(公告)号：WO2022186937A1
公开(公告)日：2022-09-09
申请号：PCT/US2022/014885
申请日：2022-02-02
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas , TADAYON, Pooya , DARMAWIKARTA, Kristof , IBRAHIM, Tarek , CHATTERJEE, Prithwish
IPC分类号： H05K1/02 , H01L23/64 , H01L49/02
摘要： An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

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