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1. 发明专利

JP2008165834A Method and apparatus for suspending execution of thread until specified memory access occurs 有权
标题翻译：用于暂停执行线程的方法和装置指定的存储器访问记录
公开(公告)号：JP2008165834A
公开(公告)日：2008-07-17
申请号：JP2008081180
申请日：2008-03-26
申请人： Intel Corp , インテルコーポレイション
发明人： MARR DEBORAH , ROGERS SCOTT , HILL DAVID , KAUSHIK SHIVNANDAN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F9/00 , G06F9/46 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/48 , G06F12/08 , G06F17/00
CPC分类号： G06F9/3009 , G06F9/30079 , G06F9/3851 , G06F9/4812 , G06F9/4843
摘要： PROBLEM TO BE SOLVED: To provide a processor, an apparatus, a method, a system and a computer readable medium for effectively temporarily suspending processing of a multi-thread processor and one thread of the multi-thread processor. SOLUTION: This invention is composed of the processor characterized by having a plurality of execution units capable of executing a plurality of threads including a first thread having a first command having a related address operand indicating a monitor address, suspending logic for suspending execution of the first thread, and a monitor for resuming the first thread in response to a memory access to the monitor address. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种处理器，装置，方法，系统和计算机可读介质，用于有效地临时挂起多线程处理器和多线程处理器的一个线程的处理。解决方案：本发明由处理器组成，其特征在于具有能够执行多个线程的多个执行单元，所述多个线程包括具有第一命令的第一线程，所述第一线程具有指示监视地址的相关地址操作数的第一命令，用于暂停执行的挂起逻辑的第一线程，以及响应于对监视器地址的存储器访问来恢复第一线程的监视器。版权所有（C）2008，JPO＆INPIT

2. 发明专利

AT478379T 未知
公开(公告)号：AT478379T
公开(公告)日：2010-09-15
申请号：AT00978857
申请日：2000-11-22
申请人： INTEL CORP
发明人： HILL DAVID , BACHAND DEREK
IPC分类号： G06F13/00 , G06F12/00 , G06F12/08 , G06F13/16 , G06F13/18

3. 发明专利

AT377797T 未知
公开(公告)号：AT377797T
公开(公告)日：2007-11-15
申请号：AT00988421
申请日：2000-12-29
申请人： INTEL CORP
发明人： SINGH GURBIR , GRENIER ROBERT , PAWLOWSKI STEPHEN , HILL DAVID , PARKER DONALD
IPC分类号： G06F13/36 , G06F13/42
摘要： A method of transmitting information over a multidrop bus from a driving agent to one or more receiving agents comprises: providing a common bus clock to both the driving agent and the one or more receiving agents; issuing a bus transaction from the driving agent to the one or more receiving agents, including: the driving agent driving multiple information elements for a request onto an address bus at a rate that is a multiple of the frequency of the bus clock; the driving agent activating a first strobe signal to identify when the one or more receiving agents should sample the information elements driven on the address bus; and transferring data from the driving agent to the one or more receiving agents comprising: the driving agent driving multiple information elements onto a data bus at a rate that is a different multiple of the frequency of the bus clock; and the driving agent activating a second strobe to identify when the one or more receiving agents should sample the information elements driven onto the data bus.

4. 发明专利

HK1075109A1 A processor and a method of suspending a thread 未知
公开(公告)号：HK1075109A1
公开(公告)日：2005-12-02
申请号：HK05107419
申请日：2005-08-24
申请人： INTEL CORP
发明人： MARR DEBORAH , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVNANDAN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F20060101 , G06F9/46 , G06F9/30 , G06F9/38
摘要： Techniques for suspending execution of a thread in a multi-threaded processor. In one embodiment, a processor includes resources that can be partitioned between multiple threads. Processor logic receives an instruction in a first thread of execution, and, in response to that instruction, relinquishes portions of the portioned resources for use by other threads.

5. 发明专利

AU2002364557A8 A method and apparatus for suspending execution of a thread until a specified memory access occurs 未知
公开(公告)号：AU2002364557A8
公开(公告)日：2003-07-24
申请号：AU2002364557
申请日：2002-12-11
申请人： INTEL CORP
发明人： KAUSHIK SHIVNANDAN , RODGERS SCOTT , CROSSLAND JAMES , HILL DAVID , MARR DEBORAH , KOUFATY DAVID
IPC分类号： G06F9/00 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/08 , G06F17/00
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

6. 发明专利

AU2002364557A1 A METHOD AND APPARATUS FOR SUSPENDING EXECUTION OF A THREAD UNTIL A SPECIFIED MEMORY ACCESS OCCURS 未知
公开(公告)号：AU2002364557A1
公开(公告)日：2003-07-24
申请号：AU2002364557
申请日：2002-12-11
申请人： INTEL CORP
发明人： CROSSLAND JAMES , KOUFATY DAVID , MARR DEBORAH , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVNANDAN
IPC分类号： G06F9/00 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/08 , G06F17/00
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

7. 发明专利

DE10297596T5 未知
公开(公告)号：DE10297596T5
公开(公告)日：2004-12-02
申请号：DE10297596
申请日：2002-12-11
申请人： INTEL CORP
发明人： MARR DEBORAH , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVANDAN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F9/00 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/08 , G06F17/00
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

8. 发明专利

GB2400947A A method and apparatus for suspending execution of a thread until a specified memory access occurs 未知
公开(公告)号：GB2400947A
公开(公告)日：2004-10-27
申请号：GB0412867
申请日：2002-12-11
申请人： INTEL CORP
发明人： MARR DEBORAH T , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVNANDAN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F9/00 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/08 , G06F17/00
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

9. 发明专利

DE10297596B4 Verfahren und Vorrichtung zum Suspendieren der Ausführung eines Threads, bis ein spezifizierter Speicherzugriff auftritt 未知
公开(公告)号：DE10297596B4
公开(公告)日：2017-09-07
申请号：DE10297596
申请日：2002-12-11
申请人： INTEL CORP
发明人： MARR DEBORAH , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVANDAN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F9/00 , G06F9/46 , G06F20060101 , G06F9/30 , G06F9/38 , G06F9/48 , G06F12/08 , G06F17/00
摘要： Techniken zum Suspendieren der Ausführung eines Threads, bis ein spezifizierter Speicherzugriff auftritt. Bei einer Ausführungsform enthält ein Prozessor mehrere Ausführungseinheiten, die mehrere Threads ausführen können. Ein erster Thread enthält eine Anweisung, die eine Überwachungsadresse spezifiziert. Suspendierungslogik suspendiert die Ausführung des ersten Threads und eine Überwachungsvorrichtung bewirkt die Wiederaufnahme des ersten Threads als Reaktion auf einen Zugriff auf die spezifizierte Überwachungsadresse.

10. 发明专利

DE10297597T5 未知
公开(公告)号：DE10297597T5
公开(公告)日：2005-01-05
申请号：DE10297597
申请日：2002-12-11
申请人： INTEL CORP
发明人： MARR DEBORAH , RODGERS SCOTT , HILL DAVID , KAUSHIK SHIVANANDEN , CROSSLAND JAMES , KOUFATY DAVID
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
摘要： Techniques for suspending execution of a thread in a multi-threaded processor. In one embodiment, a processor includes resources that can be partitioned between multiple threads. Processor logic receives an instruction in a first thread of execution, and, in response to that instruction, relinquishes portions of the portioned resources for use by other threads.

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