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1. 发明专利

JP2014059920A Instruction set architecture-based inter-sequencer communications with heterogeneous resources 审中-公开
标题翻译：具有异构资源的基于指令集架构的串行间通信
公开(公告)号：JP2014059920A
公开(公告)日：2014-04-03
申请号：JP2014000371
申请日：2014-01-06
申请人： Intel Corp , インテルコーポレイション
发明人： WANG HONG , SHEN JOHN , ZHANG HONG , HANKINS RICHARD , HAMMARLUND PER , DION ROGERS , CHINYA GAUTHAM , PATEL BAIJU , KAUSHIK SHIV , BIGBEE BRYANT , SHEAFFER GAD , TALGAM YOAV , YOSEF YUVAL , HELD JAMES P
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a method, apparatus, system that enables effective communication between instruction set architecture-based sequencers having heterogeneous resources.SOLUTION: The method comprises: directly communicating a request from a user-level application to an accelerator coupled to a first instruction sequencer via the first instruction sequencer, where the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer; providing the request to the accelerator via an exo-skeleton associated with the accelerator; and performing a first function in the accelerator in response to the request in parallel with a second function in the first instruction sequencer.
摘要翻译：要解决的问题：提供一种使得能够在具有异构资源的指令集体系结构的定序器之间有效通信的方法，装置，系统。解决方案：该方法包括：将来自用户级应用的请求直接传达到耦合到所述第一指令定序器经由所述第一指令定序器，其中所述加速器包括相对于所述第一指令定序器的异质资源; 通过与加速器相关联的外部骨架向加速器提供请求; 以及响应于与第一指令定序器中的第二功能并行的请求在加速器中执行第一功能。

2. 发明专利

JP2011175669A Method and apparatus for speculative execution of uncontended lock instruction 审中-公开
标题翻译：用于不连续锁定指令的频域执行的方法和装置
公开(公告)号：JP2011175669A
公开(公告)日：2011-09-08
申请号：JP2011102812
申请日：2011-05-02
申请人： Intel Corp , インテルコーポレイション
发明人： SAHA BRATIN , MERTEN MATTHEW C , HAMMARLUND PER
IPC分类号： G06F9/38 , G06F9/52 , G06F12/08
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for executing lock instructions speculatively in an out-of-order processor.
SOLUTION: In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在乱序处理器中推测地执行锁定指令的方法和装置。解决方案：在一个实施例中，预测给定的锁定指令是否将被实际地竞争。如果不是，则锁定指令可以被视为具有可以推测地执行的正常负载微操作。监视器逻辑可能会查找锁定指令实际上有争议的迹象。如果没有发现这样的指示，则与锁定指令相对应的投机负载微操作和其他微操作可能会退出。然而，如果事实上发现这样的指示，则可以重新启动锁定指令，并且可以更新预测机制。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010044770A Queued lock using monitor-memory wait 审中-公开
标题翻译：使用监视器等待的QUEUED锁定
公开(公告)号：JP2010044770A
公开(公告)日：2010-02-25
申请号：JP2009211907
申请日：2009-09-14
申请人： Intel Corp , インテルコーポレイション
发明人： HAMMARLUND PER , CROSSLAND JAMES , AGGARWAL ANIL , KAUSHIK SHIVNANDAN
IPC分类号： G06F9/50 , G06F9/38 , G06F9/46 , G06F9/52 , G06F12/00 , G06F12/08 , G06F12/14
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： PROBLEM TO BE SOLVED: To monitor locks for one or more processors waiting for locks. SOLUTION: A node associated with a contended lock is monitored. A processor core waiting for the contended lock is specified, and then, put to a sleep state until an event occurs. Processing resources concerning the processor core in the sleep state are relinquished. The relinquished processing resources are re-assigned to a processor core in a non-sleep state in order to use during the sleep state of the sleeping processor core. When the event occurs, the processor core is exited from the sleep state, and the control of the relinquished processing resources is restarted from the processor core in the non-sleep state. Then, the monitoring of the node is stopped. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：监视一个或多个等待锁的处理器的锁。
解决方案：监控与竞争锁相关联的节点。指定等待有争议的锁的处理器核心，然后进入睡眠状态，直到发生事件。处理处于休眠状态的处理器核心的资源被放弃。放弃的处理资源被重新分配给处于非睡眠状态的处理器核心，以便在休眠处理器核心的睡眠状态期间使用。当事件发生时，处理器核心从休眠状态退出，并且在非睡眠状态下从处理器核心重新启动放弃处理资源的控制。然后，停止对节点的监视。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2007249971A Synchronization of recency information in inclusive cache hierarchy 有权
标题翻译：包含高速缓存中的记录信息同步
公开(公告)号：JP2007249971A
公开(公告)日：2007-09-27
申请号：JP2007063584
申请日：2007-03-13
申请人： Intel Corp , インテルコーポレイション
发明人： SHANNON CHRISTOPHER , SINGHAL RONAK , HAMMARLUND PER , GARTLER HERMANN , HINTON GLENN
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/123
摘要： PROBLEM TO BE SOLVED: To provide a method, a device, an object and a system for improving performance by reducing the possibility of eliminating a cache line of a lower-level cache frequently accessed by a processor from a higher-level cache.
SOLUTION: The method includes the steps for: receiving a cache access request for data present in a lower-level cache line of the lower-level cache; and sending recency information regarding the lower-level cache line to a higher-level cache integrated in the lower-level cache.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种方法，设备，对象和系统，用于通过降低从高级缓存中消除由处理器频繁访问的低级缓存的高速缓存线的可能性来提高性能。解决方案：该方法包括以下步骤：接收对存在于下级高速缓存的下级高速缓存行中的数据的高速缓存访问请求; 以及将关于下级高速缓存线的新近度信息发送到集成在下级高速缓存中的高级缓存。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2011227934A Primitives for expanding execution of speculations at thread level 有权
标题翻译：扩展在螺纹级别执行规范的主旨
公开(公告)号：JP2011227934A
公开(公告)日：2011-11-10
申请号：JP2011177640
申请日：2011-08-15
申请人： Intel Corp , インテルコーポレイション
发明人： QUINN JACOBSON , WANG HONG , JOHN SHEN , CHINYA GOTHAM , HAMMARLUND PER , ZOU SHANG , BRYANT BIGBEE , SHIVNANDAN KAUSHIK
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： PROBLEM TO BE SOLVED: To provide a processor than can include an address monitoring table and an atomic updating table for supporting speculative threading.SOLUTION: A processor that can include one or more registers for maintaining a status relating to the execution of speculative threading, and can support one or more of primitives (commands for writing a status into a register, commands for triggering a commitment to buffered memory updating, commands for reading a status out of a status register and/or commands for clearing one of status bits related to trap/exception/interruption processing).
摘要翻译：要解决的问题：提供一种处理器，可以包括地址监视表和用于支持推测线程的原子更新表。解决方案：一种处理器，其可以包括一个或多个寄存器，用于维持与推测线程的执行有关的状态，并且可以支持一个或多个原语（用于将状态写入寄存器的命令，用于触发承诺的命令缓冲存储器更新，用于从状态寄存器读出状态的命令和/或用于清除与陷阱/异常/中断处理相关的状态位之一的命令）。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2013168168A Primitives to enhance thread-level speculation 审中-公开
标题翻译：提高螺纹水准仪的主要原则
公开(公告)号：JP2013168168A
公开(公告)日：2013-08-29
申请号：JP2013083679
申请日：2013-04-12
申请人： Intel Corp , インテルコーポレイション
发明人： QUINN JACOBSON , WANG HONG , JOHN SHEN , CHINYA GOTHAM , HAMMARLUND PER , ZOU SHANG , BIGBEE BRYANT , SHIVNANDAN KAUSHIK
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F12/00
CPC分类号： G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： PROBLEM TO BE SOLVED: To provide a processor which may include an address monitor table and an atomic update table to support speculative threading.SOLUTION: The processor may also include one or more registers to maintain a state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction for writing to a register of the state, an instruction for triggering commitment of buffered memory updates, an instruction for reading a status register of the state, and/or an instruction for clearing one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
摘要翻译：要解决的问题：提供一种处理器，其可以包括地址监视表和原子更新表以支持推测性线程。解决方案：处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。处理器可以支持以下一个或多个原语：用于写入状态寄存器的指令，用于触发缓冲存储器更新的承诺的指令，用于读取状态的状态寄存器的指令和/或用于清除与陷阱/异常/中断处理相关联的状态位之一。还描述和要求保护其他实施例。

7. 发明专利

JP2011146077A Instruction set architecture-based inter-sequencer communication with heterogeneous resource 审中-公开
标题翻译：具有异构资源的基于指令集架构的串行间通信
公开(公告)号：JP2011146077A
公开(公告)日：2011-07-28
申请号：JP2011101385
申请日：2011-04-28
申请人： Intel Corp , インテルコーポレイション
发明人： WANG HONG , SHEN JOHN , ZHANG HONG , HANKINS RICHARD , HAMMARLUND PER , RODGERS DION , CHINYA GAUTHAM , PATEL BAIJU , KAUSHIK SHIV , BIGBEE BRYANT , SHEAFFER GAD , TALGAM YOAV , YOSEF YUVAL , HELD JAMES P
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2007183943A Communication between instruction set architecture base sequencer by heterogeneous resources 审中-公开
标题翻译：通过异构资源指定设置架构基准序列器之间的通信
公开(公告)号：JP2007183943A
公开(公告)日：2007-07-19
申请号：JP2006348294
申请日：2006-12-25
申请人： Intel Corp , インテルコーポレイション
发明人： WANG HONG , SHEN JOHN , ZHANG HONG , HANKINS RICHARD , HAMMARLUND PER , RODGERS DION , CHINYA GAUTHAM , PATEL BAIJU , KAUSHIK SHIV , BIGBEE BRYANT , SHEAFFER GAD , TALGAM YOAV , YOSEF YUVAL , HELD JAMES P
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a method, a device, and a system allowing effective communication between respective instruction set architecture base sequencers having heterogeneous resources. SOLUTION: This method is constructed of steps for: directly transmitting a request to an accelerator, which is connected via a first instruction sequencer and has heterogeneous resources about the first instruction sequencer, from a user level application to the first instruction sequencer; offering the request to the accelerator via an exoskeleton about the accelerator; and executing a first function in the accelerator in response to the request in parallel to a second function in the first instruction sequencer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种允许具有异构资源的各个指令集架构基本定序器之间有效通信的方法，设备和系统。解决方案：该方法由以下步骤构成：用于通过第一指令定序器将与第一指令定序器相关的异构资源从用户级应用程序直接传送到加速器的请求到第一指令定序器; 通过关于加速器的外骨骼向加速器提出要求; 以及响应于与第一指令定序器中的第二功能并行的请求，在加速器中执行第一功能。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2009151793A Compare and exchange operation using sleep-wakeup mechanism 有权
标题翻译：使用睡眠唤醒机制的比较和交换操作
公开(公告)号：JP2009151793A
公开(公告)日：2009-07-09
申请号：JP2008324669
申请日：2008-12-19
申请人： Intel Corp , インテル・コーポレーション
发明人： SAHA BRATIN , MERTEN MATTHEW , HAMMARLUND PER
IPC分类号： G06F9/52 , G06F12/00
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/526 , G06F2209/521
摘要： PROBLEM TO BE SOLVED: To provide a method, device and system for performing comparison and exchange operation by using one sleep-wakeup mechanism.
SOLUTION: According to one embodiment, one instruction in one process is executed to help acquire a lock on behalf of the processor. When the lock is unavailable to be acquired by the processor, the instruction is put to sleep until one event occurs. While the instruction is put to sleep, the memory system of the processor monitors the change of the lock value. When the lock value is tired to be changed, or the value is changed, the wakeup of the instruction put to sleep is triggered.
COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2007242003A Technique for using memory attributes 有权
标题翻译：使用存储器属性的技术
公开(公告)号：JP2007242003A
公开(公告)日：2007-09-20
申请号：JP2007028172
申请日：2007-02-07
申请人： Intel Corp , インテル・コーポレーション
发明人： JACOBSON QUINN , BRACY ANNE , WANG HONG , SHEN JOHN , HAMMARLUND PER , MERTEN MATTHEW , SRINIVAS SURESH , DOSHI KSHITIJ , CHINYA GAUTHAM , SAHA BRATIN , ADL-TABATABAI ALI-REZA , SHEAFFER GAD
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently check memory properties in a microprocessor system. SOLUTION: Attribute bits indicating that a program has recently checked that a block of memory is appropriate for the current portion of the program to access, indicating that the program has analyzed this block of memory by a performance monitoring tool, or having properties such as access right are included in a cache memory line, and correspond to only one software thread of the program having multisoftware threads. The attribute bits are used to check the memory state of an address used by the program. COPYRIGHT: (C)2007,JPO&INPIT

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