专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160233850A1 PARALLEL FILTERING METHOD AND CORRESPONDING APPARATUS 有权
标题翻译：并行滤波方法及相关装置
公开(公告)号：US20160233850A1
公开(公告)日：2016-08-11
申请号：US14785359
申请日：2013-04-19
申请人： INSTITUTE OF AUTOMATION, CHINESE ACADEMY OF SCIENCES
发明人： Donglin Wang , Leizu Yin , Yongyong Yang , Shaolin Xie , Tao Wang
IPC分类号： H03H17/02
CPC分类号： H03H17/0223 , H03H2017/0245 , H03H2218/10
摘要： The present disclosure provides a method and apparatus for parallel filtering. The apparatus comprises: a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.
摘要翻译：本公开提供了一种用于并行滤波的方法和装置。该装置包括：多粒度存储器，数据高速缓存装置，系数缓冲器广播装置，向量操作装置和命令队列装置。多粒度存储器被配置为存储要滤波的数据，滤波器系数和滤波结果数据。数据高速缓存设备被配置为缓存，读取和更新要过滤的数据。系数缓冲广播设备被配置为缓存并广播读取的滤波器系数。命令队列设备被配置为存储和输出用于并行过滤操作的操作命令队列。矢量运算装置被配置为基于要滤波的数据和输出系数数据执行矢量运算，并将运算结果写入多粒度滤波结果存储单元。该装置和方法具有快速的滤波速度，更少的访问次数，更好的使用效率，降低的功耗和广泛的应用范围。

2. 发明授权

US09966932B2 Parallel filtering method and corresponding apparatus 有权
公开(公告)号：US09966932B2
公开(公告)日：2018-05-08
申请号：US14785359
申请日：2013-04-19
申请人： Institute of Automation, Chinese Academy of Sciences
发明人： Donglin Wang , Leizu Yin , Yongyong Yang , Shaolin Xie , Tao Wang
IPC分类号： G06F17/10 , H03H17/02
CPC分类号： H03H17/0223 , H03H2017/0245 , H03H2218/10
摘要： An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.

3. 发明申请

US20160162290A1 Processor with Polymorphic Instruction Set Architecture 审中-公开
标题翻译：具有多态指令集架构的处理器
公开(公告)号：US20160162290A1
公开(公告)日：2016-06-09
申请号：US14785385
申请日：2013-04-19
申请人： INSTITUTE OF AUTOMATION, CHINESE ACADEMY OF SCIENCES
发明人： Donglin Wang , Shaolin Xie , Yongyong Yang , Leizu Yin , Lei Wang , Zijun Liu , Tao Wang , Xing Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/30
摘要： The present disclosure provides a processor having polymorphic instruction set architecture. The processor comprises a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller. The polymorphic instruction processing unit comprises at least one functional unit. The polymorphic instruction processing unit is configured to interpret and execute a polymorphic instruction and the functional unit is configured to perform specific data operation tasks. The scalar processing unit is configured to invoke the polymorphic instruction and inquire an execution state of the polymorphic instruction. The DMA controller is configured to transmit configuration information for the polymorphic instruction and transmit data required by the polymorphic instruction to the multi-granularity parallel memory. With the present disclosure, programmers can redefine a processor instruction set based on algorithm characteristics of applications after tape-out of a processor.
摘要翻译：本公开提供了具有多态指令集架构的处理器。处理器包括标量处理单元，至少一个多态指令处理单元，至少一个多粒度并行存储器和DMA控制器。多态指令处理单元包括至少一个功能单元。多态指令处理单元被配置为解释并执行多态指令，并且功能单元被配置为执行特定的数据操作任务。标量处理单元被配置为调用多态指令并查询多态指令的执行状态。 DMA控制器被配置为发送多态指令的配置信息并将多态指令所需的数据发送到多粒度并行存储器。利用本公开，程序员可以在处理器输出之后基于应用的算法特性来重新定义处理器指令集。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式