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1. 发明授权

US6141024A Generating color text 失效
标题翻译：生成彩色文本
公开(公告)号：US6141024A
公开(公告)日：2000-10-31
申请号：US792784
申请日：1997-02-03
申请人： Indra Laksono , Antonio Asaro , Carl K. Mizuyabu
发明人： Indra Laksono , Antonio Asaro , Carl K. Mizuyabu
IPC分类号： G09G5/393 , G09G5/36
CPC分类号： G09G5/393
摘要： A rasterizer is used with a processor capable of providing raster data indicative of a pattern of pixels to be formed on a display. Each pixel has an attribute represented by a data value. The rasterizer has a replicator connected to form at least two copies of the raster data. A graphics engine is connected to use the at least two copies to store the data values in a memory. An output circuit is connected to use the data values stored in the memory to form the pattern on the display.
摘要翻译：光栅化器与能够提供指示要在显示器上形成的像素的图案的光栅数据的处理器一起使用。每个像素具有由数据值表示的属性。光栅化器具有连接的复制器以形成光栅数据的至少两个副本。连接图形引擎以使用至少两个副本将数据值存储在存储器中。连接输出电路以使用存储在存储器中的数据值在显示器上形成图案。

2. 发明授权

US07543101B2 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US07543101B2
公开(公告)日：2009-06-02
申请号：US10075149
申请日：2002-02-14
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

3. 发明授权

US06546449B1 Video controller for accessing data in a system and method thereof 有权
标题翻译：用于访问系统中的数据的视频控制器及其方法
公开(公告)号：US06546449B1
公开(公告)日：2003-04-08
申请号：US09347201
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F1336
CPC分类号： G06F13/1684
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

4. 发明授权

US06633296B1 Apparatus for providing data to a plurality of graphics processors and method thereof 有权
标题翻译：用于向多个图形处理器提供数据的装置及其方法
公开(公告)号：US06633296B1
公开(公告)日：2003-10-14
申请号：US09579432
申请日：2000-05-26
申请人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
发明人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G09G5/363 , G09G2352/00 , G09G2360/06
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译：在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。系统总线连接到连接到第二和第三AGP总线的数据桥。每个AGP总线都连接到图形处理器。桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。本发明的另一方面允许在各种AGP协议部分之间进行转换

5. 发明授权

US06728820B1 Method of configuring, controlling, and accessing a bridge and apparatus therefor 有权
标题翻译：配置，控制和访问其桥及其设备的方法
公开(公告)号：US06728820B1
公开(公告)日：2004-04-27
申请号：US09579006
申请日：2000-05-26
申请人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
发明人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
IPC分类号： G06F1336
CPC分类号： G06F3/14
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译：在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。系统总线连接到连接到第二和第三AGP总线的数据桥。每个AGP总线都连接到图形处理器。桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。本发明的另一方面允许在各种AGP协议部分之间进行转换。

6. 发明授权

US06717620B1 Method and apparatus for decompressing compressed data 失效
标题翻译：用于解压缩压缩数据的方法和装置
公开(公告)号：US06717620B1
公开(公告)日：2004-04-06
申请号：US09096550
申请日：1998-06-12
申请人： Paul Chow , Allen J. Porter , David A. Strasser , Antonio Asaro , Indra Laksono , Biljana D. Simsic
发明人： Paul Chow , Allen J. Porter , David A. Strasser , Antonio Asaro , Indra Laksono , Biljana D. Simsic
IPC分类号： H04N1104
CPC分类号： H04N19/433 , H04N19/44
摘要： A method and apparatus for decompressing compressed data, which includes video data that has been compressed in accordance with the MPEG 2 standard, wherein the processing begins by retrieving components from a non-local memory at a rate that is independent of the rate in which the components were written into the non-local memory. The components include motion vectors and run/level data. As the components are retrieved from memory, the run/level data is used to produce representations of the uncompressed data. As the representations of the uncompressed data are generated, they are processed based on the motion vector data to recapture the uncompressed data. The uncompressed data is then stored in a frame buffer for subsequent display.
摘要翻译：一种用于解压缩压缩数据的方法和装置，其包括已经根据MPEG2标准被压缩的视频数据，其中该处理开始于以非速率独立于非本地存储器组件被写入非本地内存。这些组件包括运动矢量和运行/电平数据。当从存储器检索组件时，运行/级别数据用于产生未压缩数据的表示。当生成未压缩数据的表示时，将基于运动矢量数据对它们进行处理，以重新获取未压缩的数据。然后将未压缩的数据存储在帧缓冲器中用于随后的显示。

7. 发明授权

US06469703B1 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

8. 发明授权

US06339427B1 Graphics display list handler and method 有权
标题翻译：图形显示列表处理程序和方法
公开(公告)号：US06339427B1
公开(公告)日：2002-01-15
申请号：US09211637
申请日：1998-12-15
申请人： Indra Laksono , Antonio Asaro
发明人： Indra Laksono , Antonio Asaro
IPC分类号： G06T1500
CPC分类号： G06T15/005
摘要： A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.
摘要翻译：图形显示命令列表处理程序和方法请求以循环FIFO的形式分配诸如系统存储器的存储显示命令列表作为诸如主机存储器显示列表的存储器显示列表（MDL）的存储器。诸如图形处理器的处理器将主机存储器显示列表读取指针传送到主机处理器以便于图形处理器的显示列表信令。主机处理器（或其他处理器）维护写入指针，该指针指向显示列表中的最后一个主机存储器条目。读指针由图形处理器维护并写回到主处理器。

9. 发明授权

US6100906A Method and apparatus for improved double buffering 失效
标题翻译：改进双缓冲的方法和装置
公开(公告)号：US6100906A
公开(公告)日：2000-08-08
申请号：US64569
申请日：1998-04-22
申请人： Antonio Asaro , Indra Laksono , James Doyle , Gordon F. Grigor
发明人： Antonio Asaro , Indra Laksono , James Doyle , Gordon F. Grigor
IPC分类号： G09G5/36 , G09G5/39 , G09G5/393 , G09G5/399 , G06F13/00
CPC分类号： G09G5/399 , G09G5/363
摘要： A method and apparatus for improved double buffering within a computing system begins when a series of data blocks are received from a central processing unit at a rate independent of a processing rate of a recipient engine. For example, a video graphics circuit receives a series of data blocks representing video frames from the central processing unit at a rate independent of the refresh rate of the display. As the data blocks are received, the video graphics circuit queues commands of the data blocks. Typically, the commands include processing commands and a processing rate synchronize command. To process the data blocks, the co-processor pulls commands from the queued list and processes them to produce recipient data. As the co-processor is producing the recipient data, it is utilizing a first buffer. The co-processor continues to process the commands and storing the results into the first buffer until the processing rate synchronize command is detected. At this point, the co-processor pauses processing of the commands. At the beginning of the next cycle of the processing rate, the recipient data is provided from the first buffer to the recipient engine and the co-processor resumes processing of commands, which relate to another data block. As the co-processor is processing the commands of the second data block, it is utilizing a second buffer to store the processed data, i.e., the second recipient data.
摘要翻译：一种用于在计算系统内改进双缓冲的方法和装置开始于以与接收机发动机的处理速率无关的速率从中央处理单元接收一系列数据块时开始。例如，视频图形电路以与显示器的刷新率无关的速率从中央处理单元接收表示视频帧的一系列数据块。当数据块被接收时，视频图形电路对数据块的命令进行排队。通常，命令包括处理命令和处理速率同步命令。为了处理数据块，协处理器从排队列表中提取命令并处理它们以产生接收方数据。当协处理器产生接收者数据时，它正在利用第一缓冲器。协处理器继续处理命令并将结果存储到第一缓冲器中，直到检测到处理速率同步命令。此时，协处理器暂停处理命令。在处理速率的下一周期的开始，从第一缓冲器向接收者引擎提供接收者数据，并且协处理器恢复与另一个数据块有关的命令的处理。当协处理器正在处理第二数据块的命令时，它利用第二缓冲器来存储经处理的数据，即第二接收者数据。

10. 发明授权

US06789154B1 Apparatus and method for transmitting data 有权
标题翻译：用于传输数据的装置和方法
公开(公告)号：US06789154B1
公开(公告)日：2004-09-07
申请号：US09579203
申请日：2000-05-26
申请人： Brian Lee , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
发明人： Brian Lee , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
IPC分类号： G06F1314
CPC分类号： G06F13/404
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译：在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。系统总线连接到连接到第二和第三AGP总线的数据桥。每个AGP总线都连接到图形处理器。桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。本发明的另一方面允许在各种AGP协议部分之间进行转换。

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