专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140359311A1 Controlling Power Delivery To A Processor Via A Bypass 有权
标题翻译：通过旁路控制处理器的电力输送
公开(公告)号：US20140359311A1
公开(公告)日：2014-12-04
申请号：US13906652
申请日：2013-05-31
申请人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
发明人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/172 , Y02D10/22
摘要： In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个域，每个域以独立可控的电压和频率工作，多个线性稳压器各自接收来自芯片外源的第一电压并可控制以将调节电压提供给至少一个以及多个选择器，每个选择器都耦合到所述域中的一个，其中每个选择器被配置为从所述线性调节器之一提供调节电压或将旁路电压提供给相应的域。描述和要求保护其他实施例。

2. 发明申请

US20120159074A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CACHE SIZING AND CACHE OPERATING VOLTAGE MANAGEMENT FOR OPTIMAL POWER PERFORMANCE 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括动态高速缓存和高速运行电压管理，实现最佳功率性能
公开(公告)号：US20120159074A1
公开(公告)日：2012-06-21
申请号：US13336977
申请日：2011-12-23
申请人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
发明人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
摘要： Embodiments of the invention relate to increased energy efficiency and conservation by reducing and increasing an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.
摘要翻译：本发明的实施例涉及通过减少和增加可供由处理器使用的高速缓存量和提供给高速缓存和处理器的功率量来提高能量效率和节约，基于实际使用的缓存量处理器处理数据。例如，功率控制单元（PCU）可以监视最后一级高速缓存（LLC）以识别处理器正在使用的高速缓存的大小或数量来处理数据，并且基于该量来确定启发式。基于所使用的缓存的监视量和启发式，PCU引起可用于处理器的缓存的量的相应减少或增加，并且相应地降低或增加提供给高速缓存的功率量，以及到处理器。

3. 发明授权

US08713256B2 Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance 有权
标题翻译：能量效率和节能的方法，装置和系统，包括动态高速缓存大小和高速缓存操作电压管理，实现最佳功率性能
公开(公告)号：US08713256B2
公开(公告)日：2014-04-29
申请号：US13336977
申请日：2011-12-23
申请人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
发明人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
摘要： Embodiments described herein vary an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.
摘要翻译：本文描述的实施例基于处理器实际使用的缓存的量来改变可用于由处理器使用的高速缓存的数量和提供给高速缓存和处理器的功率量。例如，功率控制单元（PCU）可以监视最后一级高速缓存（LLC）以识别处理器正在使用的高速缓存的大小或数量来处理数据，并且基于该量来确定启发式。基于所使用的缓存的监视量和启发式，PCU引起可用于处理器的缓存的量的相应减少或增加，并且相应地降低或增加提供给高速缓存的功率量，以及到处理器。

4. 发明授权

US09075741B2 Dynamic error handling using parity and redundant rows 有权
标题翻译：使用奇偶校验和冗余行的动态错误处理
公开(公告)号：US09075741B2
公开(公告)日：2015-07-07
申请号：US13327845
申请日：2011-12-16
申请人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
发明人： Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
IPC分类号： G06F11/00 , G06F11/10 , H03M13/09 , H04L1/00 , H03M13/11
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1008 , G06F11/1076 , H03M13/09 , H03M13/11 , H04L1/0057
摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
摘要翻译：公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。存储结构是存储多个数据值。奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。错误存储空间是存储奇偶校验错误检测的指示。错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

5. 发明授权

US08448010B2 Increasing memory bandwidth in processor-based systems 有权
标题翻译：在基于处理器的系统中增加内存带宽
公开(公告)号：US08448010B2
公开(公告)日：2013-05-21
申请号：US12570137
申请日：2009-09-30
申请人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
发明人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
IPC分类号： G06F1/04 , G11C8/16
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要： The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译：可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。作为一个例子，在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中，可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量。

6. 发明授权

US08345491B2 Memory cell write 有权
标题翻译：存储单元写
公开(公告)号：US08345491B2
公开(公告)日：2013-01-01
申请号：US13282331
申请日：2011-10-26
申请人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
发明人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/419
摘要： Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：存储单元的实施例包括被配置为提供第一电源电压和第二电源电压的电压模块，数据节点编程模块，被配置为接收第一电源电压并且至少部分地基于写数据线来编程数据节点以及互补数据节点编程模块，其被配置为接收所述第二电源电压并且至少部分地基于互补写入数据线来编程互补数据节点，其中所述电压模块被配置为使得所述第一电源电压基本上不同于第二电源电压在存储器件被编程期间一段时间。也可以公开和要求保护附加的变型和实施例。

7. 发明申请

US20120198208A1 SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD 有权
标题翻译：共享功能多点ROM设备和方法
公开(公告)号：US20120198208A1
公开(公告)日：2012-08-02
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

8. 发明授权

US09336008B2 Shared function multi-ported ROM apparatus and method 有权
标题翻译：共享功能多端口ROM设备和方法
公开(公告)号：US09336008B2
公开(公告)日：2016-05-10
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30 , G06F9/38 , G06F7/544
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

9. 发明申请

US20110078485A1 Increasing Memory Bandwidth in Processor-Based Systems 有权
标题翻译：在基于处理器的系统中增加内存带宽
公开(公告)号：US20110078485A1
公开(公告)日：2011-03-31
申请号：US12570137
申请日：2009-09-30
申请人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
发明人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
IPC分类号： G06F1/04
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要： The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译：可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。作为一个例子，在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中，可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量。

10. 发明授权

US07155574B2 Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory 失效
标题翻译：展望未来的LRU阵列更新方案，以最大限度地减少顺序存取的内存中的破坏
公开(公告)号：US07155574B2
公开(公告)日：2006-12-26
申请号：US11414541
申请日：2006-05-01
申请人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
发明人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F12/00
CPC分类号： G06F9/3808 , G06F12/123 , G06F12/127
摘要： A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set from a sequentially accessed memory; selecting a victim way for the selected victim set; reading a next way pointer from a trace line of a trace currently stored in the selected victim way, if the selected victim way has the next way pointer; and writing a next line of the new trace into the selected victim way over the trace line of the currently stored trace. The method also includes forcing a replacement algorithm of next set to select a victim way of the next set using the next way pointer, if the trace line of the currently stored trace is not an active trace tail line.
摘要翻译：一种高速存储器管理技术，其使顺序访问的存储器中的电路最小化，包括但不限于例如跟踪高速缓存。该方法包括从顺序访问的存储器中选择一个受害者集合; 选择所选受害者集合的受害方式; 如果所选择的受害者方式具有下一个方向指针，则从当前存储在所选择的受害者方式中的跟踪的跟踪行读取下一个方向指针; 并通过当前存储的轨迹的轨迹线将新轨迹的下一行写入所选的受害者方式。该方法还包括，如果当前存储的跟踪的跟踪线不是活动跟踪尾线，则使用下一个方向指针强制下一集合的替换算法来选择下一集合的受害方式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式