专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08448010B2 Increasing memory bandwidth in processor-based systems 有权
标题翻译：在基于处理器的系统中增加内存带宽
公开(公告)号：US08448010B2
公开(公告)日：2013-05-21
申请号：US12570137
申请日：2009-09-30
申请人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
发明人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
IPC分类号： G06F1/04 , G11C8/16
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要： The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译：可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。作为一个例子，在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中，可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量。

2. 发明申请

US20110078485A1 Increasing Memory Bandwidth in Processor-Based Systems 有权
标题翻译：在基于处理器的系统中增加内存带宽
公开(公告)号：US20110078485A1
公开(公告)日：2011-03-31
申请号：US12570137
申请日：2009-09-30
申请人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
发明人： Satish K. Damaraju , Subramaniam Maiyuran , Anupama Ambardar , Arindrajit Ghosh
IPC分类号： G06F1/04
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要： The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译：可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。作为一个例子，在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中，可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量。

3. 发明申请

US20120198208A1 SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD 有权
标题翻译：共享功能多点ROM设备和方法
公开(公告)号：US20120198208A1
公开(公告)日：2012-08-02
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

4. 发明授权

US09336008B2 Shared function multi-ported ROM apparatus and method 有权
标题翻译：共享功能多端口ROM设备和方法
公开(公告)号：US09336008B2
公开(公告)日：2016-05-10
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30 , G06F9/38 , G06F7/544
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

5. 发明授权

US07155574B2 Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory 失效
标题翻译：展望未来的LRU阵列更新方案，以最大限度地减少顺序存取的内存中的破坏
公开(公告)号：US07155574B2
公开(公告)日：2006-12-26
申请号：US11414541
申请日：2006-05-01
申请人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
发明人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F12/00
CPC分类号： G06F9/3808 , G06F12/123 , G06F12/127
摘要： A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set from a sequentially accessed memory; selecting a victim way for the selected victim set; reading a next way pointer from a trace line of a trace currently stored in the selected victim way, if the selected victim way has the next way pointer; and writing a next line of the new trace into the selected victim way over the trace line of the currently stored trace. The method also includes forcing a replacement algorithm of next set to select a victim way of the next set using the next way pointer, if the trace line of the currently stored trace is not an active trace tail line.
摘要翻译：一种高速存储器管理技术，其使顺序访问的存储器中的电路最小化，包括但不限于例如跟踪高速缓存。该方法包括从顺序访问的存储器中选择一个受害者集合; 选择所选受害者集合的受害方式; 如果所选择的受害者方式具有下一个方向指针，则从当前存储在所选择的受害者方式中的跟踪的跟踪行读取下一个方向指针; 并通过当前存储的轨迹的轨迹线将新轨迹的下一行写入所选的受害者方式。该方法还包括，如果当前存储的跟踪的跟踪线不是活动跟踪尾线，则使用下一个方向指针强制下一集合的替换算法来选择下一集合的受害方式。

6. 发明授权

US10297001B2 Reduced power implementation of computer instructions 有权
公开(公告)号：US10297001B2
公开(公告)日：2019-05-21
申请号：US14583300
申请日：2014-12-26
申请人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
发明人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
IPC分类号： G06T1/20 , G09G5/00 , G06T15/80 , G09G5/36 , G06F7/00 , G06F9/30
摘要： Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

7. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

8. 发明授权

US09612835B2 MFENCE and LFENCE micro-architectural implementation method and system 有权
公开(公告)号：US09612835B2
公开(公告)日：2017-04-04
申请号：US13619919
申请日：2012-09-14
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

9. 发明申请

US20050138341A1 Method and apparatus for a stew-based loop predictor 有权
标题翻译：一种基于炖菜的循环预测器的方法和装置
公开(公告)号：US20050138341A1
公开(公告)日：2005-06-23
申请号：US10739689
申请日：2003-12-17
申请人： Subramaniam Maiyuran , Peter Smith , Stephan Jourdan
发明人： Subramaniam Maiyuran , Peter Smith , Stephan Jourdan
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/325 , G06F9/3808 , G06F9/3844
摘要： A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.
摘要翻译：公开了一种用于预测环路结束的环路预测器的方法和装置。在一个实施例中，环路预测器可以具有预测计数器，以保持预测计数，该预测计数表示在给定循环的执行期间预测器炖值将重复的预期次数。循环预测器还可以具有一个或多个运行计数器，以在执行当前循环期间保持炖煮值重复的次数的计数。当计数器值匹配时，预测器可以发出循环结束的预测。

10. 发明授权

US06665775B1 Cache dynamically configured for simultaneous accesses by multiple computing engines 有权
标题翻译：缓存动态配置为同时访问多个计算引擎
公开(公告)号：US06665775B1
公开(公告)日：2003-12-16
申请号：US09667688
申请日：2000-09-22
申请人： Subramaniam Maiyuran , Salvador Palanca
发明人： Subramaniam Maiyuran , Salvador Palanca
IPC分类号： G06F1208
CPC分类号： G06F12/0848 , G06F12/084 , G06F12/0846
摘要： A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.
摘要翻译：缓存具有单个移植单元的阵列，并且可由多个计算引擎同时动态访问。在另一实施例中，高速缓存还具有包括第一地址输入，第二地址输入和共享模式输入的标签阵列，以及电耦合到标签阵列的数据阵列，并且包括第一地址输入，第二地址输入，和共享模式输入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式