会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Wireless modem, modulator, and demodulator
    • 无线调制解调器,调制器和解调器
    • US20070237246A1
    • 2007-10-11
    • US11496897
    • 2006-08-01
    • In Gi LimHyung Il ParkYoung Seok BaekHyuk KimTae Joon KimKyung Soo KimIk Soo EoHee Bum Jung
    • In Gi LimHyung Il ParkYoung Seok BaekHyuk KimTae Joon KimKyung Soo KimIk Soo EoHee Bum Jung
    • H04K1/10
    • H04L27/2662H04L1/0041H04L1/0045H04L1/0071H04L5/06H04L27/2657
    • A wireless modem is mounted to a terminal for wireless communication, and specifically controls an internal drive clock to reduce power consumption in an active mode. The wireless modem includes: a wireless core module for transmitting and receiving a radio signal; a modulator for converting data to be transmitted into a wireless transmission signal and transmitting the converted signal to the wireless core module; a demodulator for converting the signal received from the wireless core module into reception data; a synchronizer for synchronizing the signal received from the wireless core module; and a clock controller for generating a drive clock of each of the modulator, the demodulator, and the synchronizer. A low power clock controller is divided into six main functional blocks of a synchronizer, an analog controller, a modulator, a channel decoder, a demodulator, and a channel encoder, and has a feature that a clock is input only when a main functional block operates. As a result, it is possible to minimize power consumption caused by clock switching when an Orthogonal Frequency Division Multiplexing Access (OFDMA) mobile station modem operates in an active mode through the clock controller.
    • 无线调制解调器被安装到用于无线通信的终端,并且具体地控制内部驱动时钟以降低活动模式中的功耗。 无线调制解调器包括:用于发送和接收无线电信号的无线核心模块; 用于将要发送的数据转换成无线发送信号并将转换的信号发送到无线核心模块的调制器; 解调器,用于将从无线核心模块接收的信号转换为接收数据; 用于使从所述无线核心模块接收的信号同步的同步器; 以及时钟控制器,用于产生调制器,解调器和同步器中的每一个的驱动时钟。 低功率时钟控制器被分为同步器,模拟控制器,调制器,信道解码器,解调器和信道编码器的六个主要功能块,并且具有仅当主功能块 操作。 结果,当正交频分复用接入(OFDMA)移动台调制解调器通过时钟控制器以活动模式操作时,可以最小化由时钟切换引起的功率消耗。
    • 2. 发明授权
    • Blind channel estimation in an orthogonal frequency division multiplexing system
    • 正交频分复用系统盲信道估计
    • US07929620B2
    • 2011-04-19
    • US11634276
    • 2006-12-05
    • Tae Joon KimIk Soo EoHee Bum Jung
    • Tae Joon KimIk Soo EoHee Bum Jung
    • H04L27/28H04J11/00
    • H04L25/0238H04L25/0212H04L25/0248
    • A method for stable channel estimation to increase frequency band efficiency that is lost by using a pilot, and to reduce the complexity and the sensitivity to channel zero. The method includes generating an i-th symbol block Si including N carriers, performing an inverse fast Fourier transform (IFFT) operation on the i-th symbol block, and forming an orthogonal frequency division multiplexing (OFDM) symbol block. The method also includes attaching a guard interval sample in front of the i-th OFDM symbol block Ui and forming at least one OFDM symbol block Ui,cp. The method further includes modeling the formed OFDM symbol block Ui,cp with a channel finite impulse response (FIR) filter and estimating channel impulse response using signals yi received through a channel.
    • 一种用于稳定信道估计的方法,以增加使用导频丢失的频带效率,并降低对信道零的复杂度和灵敏度。 该方法包括生成包括N个载波的第i个符号块Si,对第i个符号块执行快速傅里叶逆变换(IFFT),并形成正交频分复用(OFDM)符号块。 该方法还包括在第i个OFDM符号块Ui的前面附加保护间隔样本并形成至少一个OFDM符号块U 1,c p。 该方法还包括使用信道有限脉冲响应(FIR)滤波器对形成的OFDM符号块Ui,cp进行建模,并且使用通过信道接收的信号y i来估计信道脉冲响应。
    • 4. 发明申请
    • Method for blind channel estimation
    • 盲信道估计方法
    • US20070133700A1
    • 2007-06-14
    • US11634276
    • 2006-12-05
    • Tae Joon KimIk Soo EoHee Bum Jung
    • Tae Joon KimIk Soo EoHee Bum Jung
    • H04K1/10H04B1/10
    • H04L25/0238H04L25/0212H04L25/0248
    • Provided is a method for channel estimation increasing frequency band efficiency lost by using a pilot, and reducing sensitivity to channel zero, instability, and complexity. The method includes the steps of: (a) generating an i-th symbol block Si including N carriers; (b) performing an inverse fast Fourier transform (IFFT) operation on the i-th symbol block and forming an orthogonal frequency division multiplexing (OFDM) symbol block; (c) attaching a guard interval sample in front of the i-th OFDM symbol block Ui and forming at least one OFDM symbol block Ui,cp; and (d) modeling the formed OFDM symbol block Ui,cp with a channel finite impulse response (FIR) filter h and noise v and estimating channel impulse response using signals yi received through a channel.
    • 提供了一种用于信道估计的方法,其通过使用导频来增加频带效率损失,并降低对信道零的灵敏度,不稳定性和复杂性。 该方法包括以下步骤:(a)产生包括N个载波的第i个符号块S i i; (b)对第i个符号块执行快速傅里叶逆变换(IFFT),形成正交频分复用(OFDM)符号块; (c)在第i个OFDM符号块U 1 i前面附加保护间隔样本,并形成至少一个OFDM符号块U i,c p; 以及(d)利用信道有限脉冲响应(FIR)滤波器h和噪声v对所形成的OFDM符号块U i,c p进行建模,并使用通过信道接收的信号y i来估计信道脉冲响应。
    • 5. 发明授权
    • Synchronizing circuit
    • 同步电路
    • US5974102A
    • 1999-10-26
    • US929692
    • 1997-09-15
    • Ik Soo EoKwang Il YeonIn Gi Lim
    • Ik Soo EoKwang Il YeonIn Gi Lim
    • H03K19/003G06F5/06H04L7/00H04L7/02
    • H04L7/02G06F5/06H04L7/0008
    • In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.
    • 在单片机和数字信号处理块在一个芯片中一起使用的情况下,存在当从一个块向另一个块发送信号时时钟的同步彼此不一致的问题。 另外,当在输入信号变化期间激活参考时钟时,发生了不完整的间隔。 因此,为了解决上述问题,本发明公开了一种使用由NAND门构成的锁存电路(“RS”)同步异步输入数据和参考时钟的同步电路,由此解决了 不完整间隔发生。
    • 7. 发明授权
    • Multi-input multi-output system and method for demodulating a transmitting vector in a receiver of the system
    • 用于解调系统的接收机中的发射矢量的多输入多输出系统和方法
    • US07787555B2
    • 2010-08-31
    • US11739209
    • 2007-04-24
    • Tae Joon KimIk Soo EoHyoun Kuk KimHyun Cheol Park
    • Tae Joon KimIk Soo EoHyoun Kuk KimHyun Cheol Park
    • H04K1/10H04L27/28H04L1/02H04B7/02H04B7/08
    • H04B7/0434
    • Provided is a receiver of a multi-input multi-output system using multiple antennas, the receiver including: a first multiplying unit for multiplying a vector r received via the antenna by a Hermitian matrix Q; a candidate transmitting vector generating unit for detecting a signal on a lowest modulation order transmitting antenna from the received vector y output from the first multiplying unit, creating as many symbol candidates as the modulation order of the detected signal, and generating a candidate transmitting vector using each symbol candidate; a transmitting vector determining unit for obtaining a distance between each candidate transmitting vector generated by the candidate transmitting vector generating unit and the received vector y to determine a final transmitting vector; and a demodulating unit for demodulating the final transmitting vector determined by the transmitting vector determining unit. Since the receiver detects a transmitting vector with reference to a signal on a lowest modulation order transmitting antenna, the receiver can have a simpler structure.
    • 提供了一种使用多个天线的多输入多输出系统的接收机,所述接收机包括:第一乘法单元,用于将通过所述天线接收的矢量r乘以Hermitian矩阵Q; 候选发射矢量产生单元,用于从从第一乘法单元输出的接收矢量y中检测最低调制阶发射天线上的信号,创建与检测信号的调制阶数一样多的符号候选,并使用 每个符号候选人; 发送矢量确定单元,用于获得由候选发射矢量生成单元生成的每个候选发射矢量与接收矢量y之间的距离,以确定最终发射矢量; 以及解调单元,用于解调由发送矢量确定单元确定的最终发送矢量。 由于接收机参考最低调制阶发射天线上的信号检测发射矢量,所以接收机可以具有更简单的结构。
    • 8. 发明授权
    • Apparatus and method for transmitting data in multi-input multi-output system
    • 用于在多输入多输出系统中传输数据的装置和方法
    • US07738843B2
    • 2010-06-15
    • US11739175
    • 2007-04-24
    • Tae Joon KimIk Soo EoHyoun Kuk KimHyun Chul Park
    • Tae Joon KimIk Soo EoHyoun Kuk KimHyun Chul Park
    • H04B1/02H04B1/04H01Q11/12H04M1/00
    • H04W52/42
    • Provided is a transmitter for a multi-input multi-output system including: a memory for storing a modulation system and power allocation coefficient for each antenna; a modulating unit for modulating data to be transmitted using the modulation system for each antenna stored in the memory when the data to be transmitted is input; and a power adjusting unit for adjusting the power according to the power allocation coefficient for each antenna stored in the memory to transmit the data to be transmitted, modulated at the modulating unit, via a corresponding antenna. A higher performance gain can be provided compared to a conventional open loop V-BLAST system by using a different modulation system and power for each antenna of a transmitter.
    • 提供一种用于多输入多输出系统的发射机,包括:存储器,用于存储每个天线的调制系统和功率分配系数; 调制单元,用于当输入要发送的数据时,使用存储在存储器中的每个天线的调制系统调制要发送的数据; 以及功率调整单元,用于根据存储在存储器中的每个天线的功率分配系数来调整功率,以经由相应的天线发送在调制单元调制的要发送的数据。 与传统的开环V-BLAST系统相比,通过使用不同的调制系统和发射机的每个天线的功率,可以提供更高的性能增益。
    • 9. 发明授权
    • Hadamard code generation circuit
    • 哈达玛码生成电路
    • US6069574A
    • 2000-05-30
    • US138545
    • 1998-08-24
    • Ik Soo EoKwang Il YeonKyung Soo Kim
    • Ik Soo EoKwang Il YeonKyung Soo Kim
    • H03K3/84H04J11/00H04J13/00H04J13/12H04L23/00H03M7/00G06K9/36G06F15/332
    • H04J13/0048H04J13/10H04B1/707
    • A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.-- 0 signal and a carry-out signal are ANDed and outputting higher bit signals C4, C3 and C2; a 4th hadamard code generator for logically processing a lower 2-bit output signal from the 2-bit counter and a lower 2-bit index value from the 6-bit register and generating a 4-th hadamard code; a 12th paley code generator for generating a 12th paley code using an output signal from the counter and the FORCE.sub.-- 0.sub.-- DEL signal and the ALL.sub.-- ZERO signal; and a 48th hadamard code generator for logically processing a 4th hadamard code and a 12th paley code and generating a 48th hadamard code.
    • 公开了一种hasamard代码生成电路。 该电路包括一个启动复位信号发生器,当来自6位参考计数器的6位输出信号REF-C,较高的4位索引输出信号H(5:2)为 6位寄存器和来自接地电路的2位值相同; 一个“0”值分配单元,用于当来自6位的4位输出信号REF-C(5:2)时输出用于强制分配第0列的所有值的FORCE-0-DEL信号为“0” 参考计数器和来自接地电路的4位值相同; 用于接收起始复位信号的2位计数器和外部时钟信号,输出最低位信号C1和C0并输出进位信号; 根据反相FORCE-0信号和进位信号进行AND运算并输出较高位信号C4,C3和C2的4位计数器; 用于逻辑处理来自2位计数器的较低2位输出信号和来自6位寄存器的较低2位索引值的第4个哈达马斯代码发生器,并生成第4个哈达玛码; 用于使用来自计数器的输出信号和FORCE-0-DEL信号和ALL-ZERO信号来产生第12个Paley码的第12个Paley码发生器; 以及第48个hasamard代码生成器,用于逻辑处理第4个hadamard代码和第12个paley代码,并生成第48个hasamard代码。