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1. 发明专利

JP2014049768A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014049768A
公开(公告)日：2014-03-17
申请号：JP2013180908
申请日：2013-09-02
申请人： Imec , アイメックImec , Taiwan Semiconductor Manufacturing Company Ltd , タイワン・セミコンダクター・マニュファクチャリング・カンパニー・リミテッドTaiwan Semiconductor Manufacturing Company Ltd.
发明人： LIESBETH WITTERS , VOS RITA , BRUNCO DAVID , VAN DAL MARCUS JOHANNES HENRICUS
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28255 , H01L21/28518 , H01L21/76814 , H01L29/165 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： PROBLEM TO BE SOLVED: To provide an improved method by a germanidation process of reducing or avoiding formation of voids in a transistor device including germanium-based channel layer, source region and drain region.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming a gate structure 5 on a germanium-containing channel layer 20 formed on a substrate and between a germanium-based source region 3 and drain region 4 which are opposite to each other with respect to the germanium-containing channel layer; a process of forming a cap layer 7 containing Si and Ge on the germanium-based source region and drain region; a process of depositing a metal layer 54 on the cap layer; performing a temperature step to alter at least a part of a cap layer to a metal germano-silicide which does not dissolve in a predetermined etchant composed to dissolve metal; and a process of selectively removing unconsumed metal from the substrate by the predetermined etchant.
摘要翻译：要解决的问题：提供一种通过锗化过程减少或避免在包括锗基通道层，源极区和漏极区的晶体管器件中形成空隙的改进方法。解决方案：一种半导体器件制造方法，包括：在形成于基板上的含锗沟道层20上形成相对于含锗沟道层彼此相对的锗系源极区域3和漏极区域4之间的栅极结构5; 在锗系源极区域和漏极区域上形成含有Si和Ge的覆盖层7的工序; 在盖层上沉积金属层54的工艺; 执行温度步骤以将覆盖层的至少一部分改变为不溶于构成溶解金属的预定蚀刻剂中的金属锗硅化物; 以及通过预定蚀刻剂从衬底中选择性去除未消耗金属的工艺。

2. 发明专利

JP2014068008A Band engineered semiconductor device and method for manufacturing the same 有权
标题翻译：带工程半导体器件及其制造方法
公开(公告)号：JP2014068008A
公开(公告)日：2014-04-17
申请号：JP2013185814
申请日：2013-09-09
申请人： Imec , アイメックImec
发明人： BENJAMIN VINCENT , HELLINGS GEERT , BRUNCO DAVID
IPC分类号： H01L21/336 , H01L21/205 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/0257 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/785 , H01L29/7856
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which improves performance of new transistor architectures with respect to short channel control in order to reduce an OFF-state leakage current.SOLUTION: The disclosure is related to a band engineered semiconductor device comprising: a substrate; and a protruding structure that is formed in a recess in the substrate and is extending above the recess, having a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted-V band gap profile with a band gap value increasing gradually from a first value at outer edges of the structure to a second value, greater than the first value, in a center of the structure.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件提高了关于短沟道控制的新晶体管架构的性能，以便减少OFF状态的漏电流。解决方案：本发明涉及一种带式工程半导体器件包括：基底; 以及突出结构，其形成在所述基板的凹部中并且在所述凹部的上方延伸，具有掩埋部分和延伸部分。至少延伸部分包括具有倒V形带隙轮廓的半导体材料，其带隙值从结构的外边缘处的第一值逐渐增加到大于第一值的第二值，大于第一值结构体。

3. 发明专利

JP2009278084A Method for producing nmos and pmos devices in cmos processing 审中-公开
标题翻译：用于在CMOS处理中生产NMOS和PMOS器件的方法
公开(公告)号：JP2009278084A
公开(公告)日：2009-11-26
申请号：JP2009110592
申请日：2009-04-30
申请人： Imec , アイメックImec
发明人： BRUNCO DAVID , DE JAEGER BRICE , SEVERI SIMONE
IPC分类号： H01L21/8238 , H01L21/265 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28255 , H01L21/823807 , H01L29/165 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method for producing an Si nMOSFET device and a Ge pMOSFET device on the same semiconductor substrate.
SOLUTION: An Si active area 2 and a Ge active area 3 are formed in an Si substrate, and a gate is formed, and then an HDD, an LDD, and halos are formed. A single activation anneal that serves for both Si nMOS and Ge pMOS is utilized. By use of a Solid Phase Epitaxial Regrowth (SPER) process for Si nMOS, the thermal budget for the Si nMOS can be lowered to be compatible with Ge pMOS. Activation of Ge n-type dopants and reasonable SPER rates for Si provide a practical lower limit on temperature of 500°C, and the melting of Ge provides an upper limit of 937°C. According to a preferred embodiment, an activation anneal temperature is applied between 500°C and 900°C. Within these temperature ranges, times that are sufficient to crystallize the Si are sufficient to activate the dopants in Ge.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供在相同的半导体衬底上制造Si nMOSFET器件和Ge pMOSFET器件的方法。解决方案：在Si衬底中形成Si有源区2和Ge有源区3，形成栅极，然后形成HDD，LDD和光晕。利用了用于Si nMOS和Ge pMOS的单一激活退火。通过使用Si nMOS的固相外延生长（SPER）工艺，可以降低Si nMOS的热预算以与Ge pMOS相容。 Ge n型掺杂剂的激活和Si的合理SPER速率为500℃的温度提供了实际的下限，Ge的熔化提供了937℃的上限。根据优选实施方案，在500℃和900℃之间施加激活退火温度。在这些温度范围内，足以使Si结晶的时间足以激活Ge中的掺杂剂。版权所有（C）2010，JPO＆INPIT

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