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1. 发明授权

US09348591B2 Multi-level tracking of in-use state of cache lines 有权
标题翻译：多级跟踪缓存行的使用状态
公开(公告)号：US09348591B2
公开(公告)日：2016-05-24
申请号：US13992729
申请日：2011-12-29
申请人： Ilhyun Kim , Chen Koren , Alexandre J. Farcy , Robert L. Hinton , Choon Wei Khor , Lihu Rappoport
发明人： Ilhyun Kim , Chen Koren , Alexandre J. Farcy , Robert L. Hinton , Choon Wei Khor , Lihu Rappoport
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30079 , G06F9/30047 , G06F9/3814
摘要： This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
摘要翻译：该公开内容包括跟踪高速缓存行的使用状态以提高管道的吞吐量，从而提高处理器的性能。可以使用第一阵列中的使用中的阵列跟踪存储在指令高速缓存中的多组指令的访问数据，直到这些集合中的一个或多个的数据达到阈值条件。然后可以将第二阵列用作在使用中的阵列在将微操作插入流水线之后跟踪指令集。当微操作从管道退出时，可以清除第一个阵列。该过程可能在第二个阵列达到阈值条件之后重复。在跟踪期间，可以通过检查每个阵列中的相应位来检测用于指令行的使用状态。附加阵列也可用于跟踪使用状态。

2. 发明申请

US20130275733A1 MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES 有权
标题翻译：多级跟踪高速缓存线路的使用状态
公开(公告)号：US20130275733A1
公开(公告)日：2013-10-17
申请号：US13992729
申请日：2011-12-29
申请人： Ilhyun Kim , Chen Koren , Alexandre J. Farcy , Robert L. Hinton , Choon Wei Khor , Lihu Rappoport
发明人： Ilhyun Kim , Chen Koren , Alexandre J. Farcy , Robert L. Hinton , Choon Wei Khor , Lihu Rappoport
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30047 , G06F9/3814
摘要： This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
摘要翻译：该公开内容包括跟踪高速缓存行的使用状态以提高管道的吞吐量，从而提高处理器的性能。可以使用第一阵列中的使用中的阵列跟踪存储在指令高速缓存中的多组指令的访问数据，直到这些集合中的一个或多个的数据达到阈值条件。然后可以使用第二阵列作为使用中阵列，以便在将微操作插入流水线之后跟踪指令集。当微操作从管道退出时，可以清除第一个阵列。该过程可能在第二个阵列达到阈值条件之后重复。在跟踪期间，可以通过检查每个阵列中的相应位来检测用于指令行的使用状态。附加阵列也可用于跟踪使用状态。

3. 发明授权

US09158696B2 Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses 有权
标题翻译：通过在指令访问之前运行标签查找来隐藏指令缓存未命中延迟
公开(公告)号：US09158696B2
公开(公告)日：2015-10-13
申请号：US13992228
申请日：2011-12-29
申请人： Ilhyun Kim , Alexandre J. Farcy , Choon Wei Khor , Robert L. Hinton
发明人： Ilhyun Kim , Alexandre J. Farcy , Choon Wei Khor , Robert L. Hinton
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0875 , G06F9/3802 , G06F12/0862
摘要： This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses. This allows overlapping the ITLB and IC miss stall cycles with older instruction byte reads or older IC misses, resulting in fewer stalls than previous implementations and improved performance
摘要翻译：本公开提供了通过将ITLB和IC标签查找与IC数据（指令字节）访问分离并使ITLB和IC标签查找在IC数据之前运行来实现IC和ITLB未命中的早期，预先处理的技术和装置访问这允许ITLB和IC错过停顿周期与旧的指令字节读取或较旧的IC错误重叠，导致比以前的实现更少的停顿和改进的性能

4. 发明申请

US20140229677A1 HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD OF THE INSTRUCTION ACCESSES 有权
标题翻译：隐藏指令高速缓存通过运行TAG LOOKUPS之前的指令访问失败
公开(公告)号：US20140229677A1
公开(公告)日：2014-08-14
申请号：US13992228
申请日：2011-12-29
申请人： Ilhyun Kim , Alexandre J. Farcy , Choon Wei Khor , Robert L. Hinton
发明人： Ilhyun Kim , Alexandre J. Farcy , Choon Wei Khor , Robert L. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/3802 , G06F12/0862
摘要： This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses. This allows overlapping the ITLB and IC miss stall cycles with older instruction byte reads or older IC misses, resulting in fewer stalls than previous implementations and improved performance
摘要翻译：本公开提供了通过将ITLB和IC标签查找与IC数据（指令字节）访问分离并使ITLB和IC标签查找在IC数据之前运行来实现IC和ITLB未命中的早期，预先处理的技术和装置访问这允许ITLB和IC错过停顿周期与旧的指令字节读取或较旧的IC错误重叠，导致比以前的实现更少的停顿和改进的性能

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