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1. 发明授权

US5600268A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US5600268A
公开(公告)日：1997-02-04
申请号：US315594
申请日：1994-09-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/09448 , H01L27/0623 , H03K19/01 , H03K19/01721
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于当场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

2. 发明授权

US5239212A Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement 失效
标题翻译：具有改善放电布置的组合场效应和双极晶体管的栅极电路
公开(公告)号：US5239212A
公开(公告)日：1993-08-24
申请号：US986891
申请日：1992-12-08
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H01L27/06 , H03K19/01 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/01 , H01L27/0623 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
摘要翻译：低功耗门电路结构包括互补场效应晶体管和双极型晶体管的组合，以及放电装置，用于在场效应晶体管和双极晶体管截止时从这些晶体管放电累积的电荷。

3. 发明授权

US5001366A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US5001366A
公开(公告)日：1991-03-19
申请号：US127206
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-space consumption gate circuit structure-comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

4. 发明授权

US4829201A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4829201A
公开(公告)日：1989-05-09
申请号：US127183
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

5. 发明授权

US4890017A CMOS-BiCMOS gate circuit 失效
标题翻译： CMOS-BiCMOS门电路
公开(公告)号：US4890017A
公开(公告)日：1989-12-26
申请号：US127184
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

6. 发明授权

US4719373A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4719373A
公开(公告)日：1988-01-12
申请号：US45216
申请日：1987-04-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/60 , H03K3/33
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

7. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

8. 发明授权

US4589007A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4589007A
公开(公告)日：1986-05-13
申请号：US529764
申请日：1983-09-06
申请人： Shigeo Kuboki , Mitsuhiro Ikeda , Akihiko Takano , Yoji Nishio , Ikuro Masuda
发明人： Shigeo Kuboki , Mitsuhiro Ikeda , Akihiko Takano , Yoji Nishio , Ikuro Masuda
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L23/528 , H01L21/82 , H01L27/11807 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged adjacent to and in parallel with each other to form a basic cell line. A plurality of such basic cell lines are arranged in parallel with each other with a wiring region of a predetermined width being interleaved between adjacent basic cell lines.
摘要翻译：公开了一种半导体集成电路器件。在半导体衬底的一个主表面上形成至少具有基本晶体管器件的多个单元电池排列成一行以形成单元电池。这些单位细胞系中的至少两个彼此相邻并且平行地排列以形成基本细胞系。多个这样的基本细胞系被布置成彼此并联，具有预定宽度的布线区域在相邻的基本细胞系之间交错。

9. 发明授权

US4617648A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4617648A
公开(公告)日：1986-10-14
申请号：US669348
申请日：1984-11-08
申请人： Shigeo Kuboki , Hideo Maejima , Ikuro Masuda
发明人： Shigeo Kuboki , Hideo Maejima , Ikuro Masuda
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F11/267 , H01L21/66 , H01L21/822 , H01L27/04 , G11C13/00
CPC分类号： G06F11/2236 , G01R31/318541
摘要： A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.
摘要翻译：公开了一种半导体集成电路装置，其具备包括彼此连接形成闭环的栅极的触发电路。所述装置包括：当所述装置被诊断为检测到其中的故障时，所述装置包括：产生第一写定时信号，第二写定时信号，诊断控制信号和全部与触发器电路有关的诊断数据的装置; 连接到所述触发器电路的输出侧的第二装置，用于根据所述第一写入定时信号使所述门的闭合环路断开; 连接到所述触发器电路的输出侧的第三装置，用于根据所述第二写定时信号将所述诊断数据提供给所述触发器电路; 以及连接到触发器电路的输入侧的第四装置，用于根据诊断控制信号阻断施加到触发器电路的输入侧的信号。

10. 发明授权

US4701922A Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US4701922A
公开(公告)日：1987-10-20
申请号：US769311
申请日：1985-08-26
申请人： Shigeo Kuboki , Ikuro Masuda , Toshiaki Masuda , Terumine Hayashi
发明人： Shigeo Kuboki , Ikuro Masuda , Toshiaki Masuda , Terumine Hayashi
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L27/00
CPC分类号： G01R31/318558
摘要： An integrated circuit device comprises combinational circuits and sequential circuits. Each of the sequential circuits is provided with a (common) input control signal terminal for controlling the entry of main input terminal signals into the sequential circuit, a test data input/output terminal, a read/write signal terminal for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuit groups, and combinational circuit groups used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers. Test data are written into and read out from the sequential circuit groups under control of read/write signal lines through bus lines dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with a smaller number of steps and a small test circuit area.
摘要翻译：集成电路装置包括组合电路和顺序电路。每个顺序电路设置有（公共）输入控制信号端子，用于控制主输入端信号进入顺序电路，测试数据输入/输出端，读/写信号端，用于控制测试数据和锁存电路。集成电路器件分为顺序电路组和组合电路组，用作分配测试单元，其主要输入/输出端子组通过布线层与顺序电路组相连。在通过专用于测试的总线进行读/写信号线的控制下，将测试数据写入和读出顺序电路组。因此，以更小的步数和小的测试电路面积可以容易地获得更高的故障覆盖率。

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