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1. 发明申请

US20060091439A1 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US20060091439A1
公开(公告)日：2006-05-04
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

2. 发明授权

US07750407B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US07750407B2
公开(公告)日：2010-07-06
申请号：US11612265
申请日：2006-12-18
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

3. 发明授权

US07402868B2 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US07402868B2
公开(公告)日：2008-07-22
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

4. 发明授权

US08404541B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US08404541B2
公开(公告)日：2013-03-26
申请号：US12790578
申请日：2010-05-28
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L21/8247
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

5. 发明申请

US20080151590A1 METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING 有权
标题翻译：用于保护过程诱发电荷的方法和装置
公开(公告)号：US20080151590A1
公开(公告)日：2008-06-26
申请号：US11614053
申请日：2006-12-20
申请人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
发明人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
IPC分类号： H01L23/60 , G11C5/00
CPC分类号： H01L21/768 , G11C8/08 , G11C8/14 , H01L27/0248 , H01L29/66477 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).
摘要翻译：用于改善电荷耗散保护的半导体器件（400）包括衬底（426），半导体或导电材料层（406），一个或多个薄膜器件（408）和电荷通道器件（414）。薄膜器件（408）连接到半导体或导电层（406），并且电荷通道器件（414）耦合到薄膜器件（408）和衬底（426），并提供来自薄的薄膜器件（408）到衬底（426）以将电荷从半导体/导电层（406）耗散到衬底（426）。

6. 发明授权

US08445966B2 Method and apparatus for protection against process-induced charging 有权
标题翻译：用于防止过程引起的充电的方法和装置
公开(公告)号：US08445966B2
公开(公告)日：2013-05-21
申请号：US11614053
申请日：2006-12-20
申请人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
发明人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L21/768 , G11C8/08 , G11C8/14 , H01L27/0248 , H01L29/66477 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).
摘要翻译：用于改善电荷耗散保护的半导体器件（400）包括衬底（426），半导体或导电材料层（406），一个或多个薄膜器件（408）和电荷通道器件（414）。薄膜器件（408）连接到半导体或导电层（406），并且电荷通道器件（414）耦合到薄膜器件（408）和衬底（426），并提供来自薄的薄膜器件（408）到衬底（426）以将电荷从半导体/导电层（406）耗散到衬底（426）。

7. 发明授权

US07285827B1 Back-to-back NPN/PNP protection diodes 有权
标题翻译：背对背NPN / PNP保护二极管
公开(公告)号：US07285827B1
公开(公告)日：2007-10-23
申请号：US11194449
申请日：2005-08-02
申请人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
发明人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/0255
摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.
摘要翻译：一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。

8. 发明授权

US07573103B1 Back-to-back NPN/PNP protection diodes 有权
标题翻译：背对背NPN / PNP保护二极管
公开(公告)号：US07573103B1
公开(公告)日：2009-08-11
申请号：US11855704
申请日：2007-09-14
申请人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
发明人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
IPC分类号： H01L27/06
CPC分类号： H01L27/0266 , H01L27/0255
摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.
摘要翻译：一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱金属线。

9. 发明授权

US06906959B2 Method and system for erasing a nitride memory device 有权
标题翻译：擦除氮化物存储器件的方法和系统
公开(公告)号：US06906959B2
公开(公告)日：2005-06-14
申请号：US10306252
申请日：2002-11-27
申请人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
发明人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/14 , H01L29/7923
摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.
摘要翻译：本发明是一种擦除氮化物存储器件的方法和系统。在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。最后，电接点耦合到隔离的P阱。

10. 发明授权

US06897110B1 Method of protecting a memory array from charge damage during fabrication 有权
标题翻译：在制造期间保护存储器阵列免受电荷损伤的方法
公开(公告)号：US06897110B1
公开(公告)日：2005-05-24
申请号：US10305750
申请日：2002-11-26
申请人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
发明人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
IPC分类号： H01L21/336 , H01L21/4763 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.
摘要翻译：一种制造存储器阵列的方法，同时保护其免受电荷损坏。可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。字线形成在位线之上，并且可以具有栅极区域。接下来，在位线之上形成耦合到位线之一的第一金属区域。形成不与第一金属区电耦合的第二金属区域。然后，第一金属区域电耦合到第二金属区域。通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。此外，可以在位线和字线之间形成保险丝，以保护字线。

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