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1. 发明申请

US20090044054A1 DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
标题翻译： DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器
公开(公告)号：US20090044054A1
公开(公告)日：2009-02-12
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正衡量关键路径。

2. 发明授权

US07941772B2 Dynamic critical path detector for digital logic circuit paths 有权
标题翻译：用于数字逻辑电路路径的动态关键路径检测器
公开(公告)号：US07941772B2
公开(公告)日：2011-05-10
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状况，以及执行预定的校正衡量关键路径。

3. 发明授权

US08132136B2 Dynamic critical path detector for digital logic circuit paths 有权
标题翻译：用于数字逻辑电路路径的动态关键路径检测器
公开(公告)号：US08132136B2
公开(公告)日：2012-03-06
申请号：US11937111
申请日：2007-11-08
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状况，以及执行预定的校正衡量关键路径。本发明还涉及电路所在的设计结构。

4. 发明申请

US20090044160A1 DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
标题翻译： DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器
公开(公告)号：US20090044160A1
公开(公告)日：2009-02-12
申请号：US11937111
申请日：2007-11-08
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正衡量关键路径。本发明还涉及电路所在的设计结构。

5. 发明授权

US08291357B2 On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations 有权
标题翻译：集成了导体对的片上识别电路，每个导体具有由于工艺变化而基本上随机的短路的机会
公开(公告)号：US08291357B2
公开(公告)日：2012-10-16
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F9/45
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

6. 发明申请

US20090094566A1 DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM 审中-公开
标题翻译：芯片识别系统设计结构
公开(公告)号：US20090094566A1
公开(公告)日：2009-04-09
申请号：US12105883
申请日：2008-04-18
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06K19/067
摘要： Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了用于片上识别电路的设计结构。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

7. 发明申请

US20090091351A1 CHIP IDENTIFICATION SYSTEM AND METHOD 有权
标题翻译：芯片识别系统和方法
公开(公告)号：US20090091351A1
公开(公告)日：2009-04-09
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： H03K19/00 , H01L23/544
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

8. 发明申请

US20090132732A1 UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路SOC环境通用外围处理器系统
公开(公告)号：US20090132732A1
公开(公告)日：2009-05-21
申请号：US11942000
申请日：2007-11-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.
摘要翻译：集成电路（IC）上的通用外围处理器架构包括耦合到接口逻辑器件的第一和第二数据总线，用于实现第一和第二数据总线之间的通信，包括多个信令协议的启用接口。一个或多个处理器与第一和第二数据总线通信以管理IC上的控制功能。数据路径能够在第一和第二数据总线之间传送数据，并与数据存储设备进行通信。数据控制路径实现数据存储设备和处理器之间的通信。

9. 发明申请

US20090132747A1 STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路中SOC环境的通用外围处理器系统结构
公开(公告)号：US20090132747A1
公开(公告)日：2009-05-21
申请号：US12122289
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
IPC分类号： G06F13/14
CPC分类号： G06F13/4059 , G06F2213/0038
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括耦合到接口逻辑器件的第一和第二数据总线，用于实现第一和第二数据总线之间的通信，包括多个信令协议的启用接口。一个或多个处理器与第一和第二数据总线通信以管理IC上的控制功能。数据路径能够在第一和第二数据总线之间传送数据，并与数据存储设备进行通信。数据控制路径实现数据存储设备和处理器之间的通信。

10. 发明申请

US20080215923A1 DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) 失效
标题翻译：基于任务调度器的设计结构（交易活动 - 手动触发）
公开(公告)号：US20080215923A1
公开(公告)日：2008-09-04
申请号：US12050982
申请日：2008-03-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
IPC分类号： G06F11/30
CPC分类号： G06F17/5022 , G06F2217/14
摘要： Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要翻译：公开了用于基于任务的调试器（事务 - 事件 - 作业触发）的装置的设计结构。更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。核心连接到链接功能调试逻辑元件的互连结构。每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件。

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