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1. 发明申请

US20050036238A1 Microelectronic device with closely spaced contact studs 有权
标题翻译：具有紧密间隔的接触螺柱的微电子器件
公开(公告)号：US20050036238A1
公开(公告)日：2005-02-17
申请号：US10641949
申请日：2003-08-15
申请人： Ibro Tabakovic , Ladislav Pust , Arthur Thayer , Thu Nguyen
发明人： Ibro Tabakovic , Ladislav Pust , Arthur Thayer , Thu Nguyen
IPC分类号： G11B5/127 , G11B5/60
CPC分类号： G11B5/127
摘要： A microelectronic device includes a transducer. An overcoat layer is disposed on a transducer surface. A plurality of electrical contact pads are disposed on the overcoat layer. First and second studs that pass through the overcoat layer to connect the transducer to the electrical contact pads. The first and second studs are separated from one another by a reduced spacing distance that is free of trenching.
摘要翻译：微电子器件包括换能器。覆盖层设置在换能器表面上。多个电接触垫设置在外涂层上。穿过外涂层的第一和第二螺柱将换能器连接到电接触垫。第一和第二螺柱通过减小的没有下料的间隔距离彼此分开。

2. 发明授权

US09058860B2 Methods and apparatus for synthesizing multi-port memory circuits 有权
标题翻译：用于合成多端口存储器电路的方法和装置
公开(公告)号：US09058860B2
公开(公告)日：2015-06-16
申请号：US13434296
申请日：2012-03-29
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C11/00 , G11C7/10 , G11C8/16 , G11C11/413
CPC分类号： G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
摘要翻译：现代数字集成电路中通常需要多端口存储器电路来存储数据。多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

3. 发明授权

US08902672B2 Methods and apparatus for designing and constructing multi-port memory circuits 有权
标题翻译：多端口存储器电路的设计与构造方法
公开(公告)号：US08902672B2
公开(公告)日：2014-12-02
申请号：US13732372
申请日：2013-01-01
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian , Kartik Mohanram
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian , Kartik Mohanram
IPC分类号： G11C8/16 , G11C11/419 , G11C7/10 , G11C7/22
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C11/412
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.
摘要翻译：大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

4. 发明授权

US08779238B2 Floral dip method for transformation of camelina 失效
标题翻译：用于转化骆驼花的花卉浸渍法
公开(公告)号：US08779238B2
公开(公告)日：2014-07-15
申请号：US12933827
申请日：2009-03-19
申请人： Thu Nguyen , Xunjia Liu , Jay Derocher
发明人： Thu Nguyen , Xunjia Liu , Jay Derocher
IPC分类号： A01H5/10
CPC分类号： C12N15/8205
摘要： The present invention provides methods for transforming Camelina plants. In particular, the present invention relates to transforming Camelina sativa plants through contacting the plants to a dipping solution comprising Agrobacterium, a sugar, and a nonionic surfactant. The methods do not require a vacuum filtration step. The present invention provides, for example, useful methods for developing transformation systems for Camelina sativa that can enable manipulation of its agronomic qualities.
摘要翻译：本发明提供了转化Camelina植物的方法。特别地，本发明涉及通过使植物接触包含农杆菌，糖和非离子表面活性剂的浸渍溶液来转化Camelina sativa植物。该方法不需要真空过滤步骤。本发明提供了例如用于开发Camelina的转化系统的有用方法，其可以操纵其农艺学性质。

5. 发明申请

US20110171093A1 ACIDIC GAS REMOVAL BY AQUEOUS AMINE SOLVENTS 有权
标题翻译：酸性溶液除去酸性气体
公开(公告)号：US20110171093A1
公开(公告)日：2011-07-14
申请号：US13004606
申请日：2011-01-11
申请人： Gary Rochelle , Stephanie Freeman , Xi Chen , Thu Nguyen , Alexander Voice , Humera Rafique
发明人： Gary Rochelle , Stephanie Freeman , Xi Chen , Thu Nguyen , Alexander Voice , Humera Rafique
IPC分类号： B01D53/62 , B01F1/00
CPC分类号： B01D53/1456 , B01D53/1493 , B01D2251/80 , B01D2257/304 , B01D2257/306 , B01D2257/308 , B01D2257/504
摘要： Compositions and methods related to the removal of acidic gas. In one embodiment, compositions and methods are provided for the removal of acidic gas from a gas mixture using an aqueous amine solvent comprising water, a first amine, and a second amine, wherein the first amine contributes at least 50% by weight of the solvent's total amine concentration.
摘要翻译：与去除酸性气体相关的组成和方法。在一个实施方案中，提供组合物和方法用于使用包含水，第一胺和第二胺的含水胺溶剂从气体混合物中除去酸性气体，其中第一胺占溶剂的至少50重量％总胺浓度。

6. 发明申请

US20110047537A1 Updating client node of computing system 失效
标题翻译：更新计算系统的客户端节点
公开(公告)号：US20110047537A1
公开(公告)日：2011-02-24
申请号：US12545724
申请日：2009-08-21
申请人： Jean X. Yu , James J. Myers , Gergana V. Markova , Thu Nguyen , David M. Cannon , Kenneth E. Hannigan , James P. Smith , Colin S. Dawson
发明人： Jean X. Yu , James J. Myers , Gergana V. Markova , Thu Nguyen , David M. Cannon , Kenneth E. Hannigan , James P. Smith , Colin S. Dawson
IPC分类号： G06F9/44 , H04L9/32 , G06F9/445
CPC分类号： G06F8/61
摘要： During execution of an existing scheduling computer program on a client node, an update computer program and a self-describing automatic installation package are downloaded to the client node from a logical depot node implemented on an existing management server. Therefore, advantageously, no physical depot node or other additional computing device is needed for the client node to update itself. Execution of the update computer program is spawned on the client node from the existing scheduling computer program. As such, the update computer program inherits root access to the client node and security credentials to the management server from the scheduling computer program—advantageously, then, a user does not have to perform any laborious configuration of the client node in order to update the node. The client node ultimately updates itself using the self-describing automatic installation package, which includes all the information needed for the client node to update itself.
摘要翻译：在客户机节点上执行现有的调度计算机程序期间，将更新计算机程序和自描述自动安装包从在现有管理服务器上实现的逻辑仓库节点下载到客户端节点。因此，有利的是，客户机节点不需要物理站点节点或其他额外的计算设备来更新自身。从现有的调度计算机程序在客户机节点上产生更新计算机程序的执行。因此，更新计算机程序从调度计算机程序继承对客户端节点的根访问和对管理服务器的安全凭证 - 然后，用户不必执行客户端节点的任何费力配置，以便更新节点。客户端节点最终使用自描述自动安装软件包来自动更新，其中包括客户端节点自身更新所需的所有信息。

7. 发明授权

US07318115B2 IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic 有权
标题翻译：具有控制器的IC存储器复合器用于存储器块的集群使用套环逻辑进行I / O复用
公开(公告)号：US07318115B2
公开(公告)日：2008-01-08
申请号：US10649090
申请日：2003-08-27
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.
摘要翻译：用于降低数字特定信号处理器集成电路中的功耗的方法和装置。数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。全局内存集群到内存集群中。具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。非活动数据总线通过使用总线状态保持器保持其状态。循环缓冲器在程序循环中存储指令以避免存储器访问。功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。

8. 发明授权

US08760958B2 Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist 有权
标题翻译：用于设计和构造具有电压辅助功能的多端口存储器电路的方法和装置
公开(公告)号：US08760958B2
公开(公告)日：2014-06-24
申请号：US13421704
申请日：2012-03-15
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C8/00 , G11C8/16
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。单端读取允许内存系统同时处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到位单元格。因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

9. 发明授权

US06944087B2 Method and apparatus for off boundary memory access 失效
标题翻译：用于边界内存访问的方法和装置
公开(公告)号：US06944087B2
公开(公告)日：2005-09-13
申请号：US10076966
申请日：2002-02-15
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C8/00
摘要： Disclosed is a method and apparatus for an off boundary memory to provide off boundary memory access. The off boundary memory includes a right memory array having a plurality of right memory rows and a left memory array having a plurality of left memory rows. This forms a memory having a plurality of row lines, each row line having a right memory row and a left memory row, respectively. An off boundary row address decoder is coupled to both the right and left memory arrays and is capable of performing an off boundary memory access which includes accessing a desired plurality of memory addresses from one of a right or left memory row of a row line and from one of a left or right memory row of an adjacent row line at substantially the same time within one memory access cycle.
摘要翻译：公开了一种用于提供边界存储器访问的离岸存储器的方法和装置。离开边界存储器包括具有多个右存储器行的右存储器阵列和具有多个左存储器行的左存储器阵列。这形成具有多个行线的存储器，每行行分别具有右存储器行和左存储器行。离边界行地址解码器耦合到左和右存储器阵列，并且能够执行关闭边界存储器访问，其包括从行行的右或左存储器行中的一个访问期望的多个存储器地址，以及从在一个存储器访问周期内基本上相同的时间内相邻行行的左或右存储器行之一。

10. 发明申请

US20050076194A1 Unified instruction pipeline for power reduction in a digital signal processor integrated circuit 有权
标题翻译：用于数字信号处理器集成电路中的功率降低的统一指令流水线
公开(公告)号：US20050076194A1
公开(公告)日：2005-04-07
申请号：US10651234
申请日：2003-08-28
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
IPC分类号： G06F1/26 , G06F7/38 , G06F12/00 , G06F13/38
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.
摘要翻译：用于降低数字特定信号处理器集成电路中的功耗的方法和装置。数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。全局内存集群到内存集群中。具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。非活动数据总线通过使用总线状态保持器保持其状态。循环缓冲器在程序循环中存储指令以避免存储器访问。功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。

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