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1. 发明授权

US08902672B2 Methods and apparatus for designing and constructing multi-port memory circuits 有权
标题翻译：多端口存储器电路的设计与构造方法
公开(公告)号：US08902672B2
公开(公告)日：2014-12-02
申请号：US13732372
申请日：2013-01-01
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian , Kartik Mohanram
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian , Kartik Mohanram
IPC分类号： G11C8/16 , G11C11/419 , G11C7/10 , G11C7/22
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C11/412
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.
摘要翻译：大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

2. 发明申请

US20140104960A1 Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits 审中-公开
标题翻译：用于设计和构建高速存储器电路的方法和装置
公开(公告)号：US20140104960A1
公开(公告)日：2014-04-17
申请号：US13651698
申请日：2012-10-15
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C7/12 , G11C7/10
CPC分类号： G11C7/12 , G11C7/1042 , G11C8/16 , G11C11/419
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data.
摘要翻译：在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数字数据位。通常通过对地址进行解码来读取SRAM存储器电路，使用一组位线从寻址的存储器单元读取，从读取的存储器单元输出数据，并为后续存储器周期预充电位线。为了更快地处理存储器操作，提出了一种位线复用系统。两组位线耦合到每个存储器单元，并且每组位线用于交替存储器周期中的存储器操作。在第一存储器周期期间，第一组位线在对第二组位线进行预充电的同时访问存储器阵列。然后在第一存储器周期之后的第二存储器周期期间，第一组位线被预充电，而第二组位线访问存储器阵列以读取数据。

3. 发明申请

US20140185364A1 Methods And Apparatus For Designing And Constructing Multi-Port Memory Circuits 有权
标题翻译：用于设计和构造多端口存储器电路的方法和装置
公开(公告)号：US20140185364A1
公开(公告)日：2014-07-03
申请号：US13732372
申请日：2013-01-01
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C11/412
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.
摘要翻译：大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

4. 发明申请

US20130258757A1 Methods And Apparatus For Synthesizing Multi-Port Memory Circuits 有权
标题翻译：用于合成多端口存储器电路的方法和装置
公开(公告)号：US20130258757A1
公开(公告)日：2013-10-03
申请号：US13434296
申请日：2012-03-29
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C8/16 , G11C11/00
CPC分类号： G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
摘要翻译：现代数字集成电路中通常需要多端口存储器电路来存储数据。多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

5. 发明授权

US09058860B2 Methods and apparatus for synthesizing multi-port memory circuits 有权
标题翻译：用于合成多端口存储器电路的方法和装置
公开(公告)号：US09058860B2
公开(公告)日：2015-06-16
申请号：US13434296
申请日：2012-03-29
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C11/00 , G11C7/10 , G11C8/16 , G11C11/413
CPC分类号： G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
摘要翻译：现代数字集成电路中通常需要多端口存储器电路来存储数据。多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

6. 发明授权

US08760958B2 Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist 有权
标题翻译：用于设计和构造具有电压辅助功能的多端口存储器电路的方法和装置
公开(公告)号：US08760958B2
公开(公告)日：2014-06-24
申请号：US13421704
申请日：2012-03-15
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C8/00 , G11C8/16
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。单端读取允许内存系统同时处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到位单元格。因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

7. 发明申请

US20130242677A1 Methods and Apparatus for Designing and Constructing Multi-port Memory Circuits with Voltage Assist 有权
标题翻译：用于设计和构造具有电压辅助的多端口存储器电路的方法和装置
公开(公告)号：US20130242677A1
公开(公告)日：2013-09-19
申请号：US13421704
申请日：2012-03-15
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。单端读取允许内存系统同时处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到位单元格。因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

8. 发明授权

US08589851B2 Intelligent memory system compiler 有权
标题翻译：智能内存系统编译器
公开(公告)号：US08589851B2
公开(公告)日：2013-11-19
申请号：US12806946
申请日：2010-08-23
申请人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
发明人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0683 , G06F12/0844 , G06F12/0851 , G06F12/0855
摘要： Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.
摘要翻译：为集成电路设计存储器子系统可能是耗时且昂贵的任务。为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及存储器系统的测试套件。

9. 发明申请

US20150003148A1 Methods and Apparatus for Designing and Constructing Dual Write Memory Circuits with Voltage Assist 有权
标题翻译：用于设计和构造具有电压辅助的双写存储器电路的方法和装置
公开(公告)号：US20150003148A1
公开(公告)日：2015-01-01
申请号：US14274518
申请日：2014-05-09
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。因此，具有电压辅助的空间域复用允许单端写入来处理在单个周期中处理的两个独立的写操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

10. 发明申请

US20110145777A1 Intelligent memory system compiler 有权
标题翻译：智能内存系统编译器
公开(公告)号：US20110145777A1
公开(公告)日：2011-06-16
申请号：US12806946
申请日：2010-08-23
申请人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
发明人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0683 , G06F12/0844 , G06F12/0851 , G06F12/0855
摘要： Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.
摘要翻译：为集成电路设计存储器子系统可能是耗时且昂贵的任务。为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及存储器系统的测试套件。

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