专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

2. 发明授权

US06654834B1 Method and apparatus for data transfer employing closed loop of memory nodes 有权
标题翻译：采用闭环存储器节点进行数据传输的方法和装置
公开(公告)号：US06654834B1
公开(公告)日：2003-11-25
申请号：US09615645
申请日：2000-07-13
申请人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
发明人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
IPC分类号： G06F100
CPC分类号： G06F15/173
摘要： Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.
摘要翻译：主节点（300）和多个存储节点（301-308）之间的数据传输遵循同步固定等待时间环路总线（255）。每个存储器节点包括总线接口（311-318），其将命令，写入数据，地址和读取数据传递给循环中的下一个存储器节点。如果读取命令被指向，则每个存储器节点在指定的地址处从其存储器执行读取。如果写入命令被指向，则每个存储器节点对指定地址的存储器执行写操作。无论访问哪个存储器节点，此配置都会在发出读命令和读取数据的返回之间提供固定的等待时间。该配置可以防止返回的读取数据发生冲突。该配置保留发出的读写顺序保持读/写和写/读命令对的正确功能。该配置为每个阶段提供固定加载，而不管存储器节点的数量。因此，简化了以高速运行的大型系统的设计。

3. 发明授权

US06651083B1 Distributed service request system for providing fair arbitration using token passing scheme to resolve collisions 有权
标题翻译：分布式服务请求系统，通过令牌通过方案提供公平仲裁，以解决冲突
公开(公告)号：US06651083B1
公开(公告)日：2003-11-18
申请号：US09615172
申请日：2000-07-13
申请人： Iain Robertson , Amarjit S. Bhandal , John Keay
发明人： Iain Robertson , Amarjit S. Bhandal , John Keay
IPC分类号： G06F1336
CPC分类号： H04L12/417 , G06F13/37
摘要： A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了适用于数据传输控制器处理的传送请求总线（25），尽管在发生冲突的转移请求时导致伴随的冲突，但是多个并发传输请求。传输请求从上游传送请求节点（318）传递到下游传送请求节点（300），然后传送到具有队列（320）的传送请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

4. 发明授权

US06532533B1 Input/output system with mask register bit control of memory mapped access to individual input/output pins 有权
标题翻译：输入/输出系统具有掩码寄存器位控制，存储器映射访问各个输入/输出引脚
公开(公告)号：US06532533B1
公开(公告)日：2003-03-11
申请号：US09450889
申请日：1999-11-29
申请人： Amarjit S. Bhandal , Graham Short , Richard Simpson
发明人： Amarjit S. Bhandal , Graham Short , Richard Simpson
IPC分类号： G06F1320
CPC分类号： G06F9/30018 , G06F9/30101
摘要： A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56) has bits corresponding to each pin for driving the signal on the pin (52) to a desired value. An output enable register (58) controls output buffers (62) coupled between the output register (56) and the pins (52). A plurality of mask registers (60) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register (56), the data output register (58) and the output enable register (60) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register (60). Logic (50) accesses the data registers in view of the state of the associated mask register (60).
摘要翻译：处理装置（10）提供通用的输入/输出引脚（52），以供软件程序根据需要使用。数据输入寄存器（54）具有对应于每个引脚（52）的位，用于存储引脚上的信号值。数据输出寄存器（56）具有与每个引脚相对应的位，用于将引脚（52）上的信号驱动到期望值。输出使能寄存器（58）控制耦合在输出寄存器（56）和引脚（52）之间的输出缓冲器（62）。多个掩模寄存器（60）可以被单独设置以限定与掩模相关联的引脚的集合。通过多个地址访问数据寄存器，数据输入寄存器（56），数据输出寄存器（58）和输出使能寄存器（60）中的每一个，其中地址指定正被访问的数据寄存器和相关联的屏蔽寄存器（60）。鉴于相关屏蔽寄存器（60）的状态，逻辑（50）访问数据寄存器。

5. 发明授权

US06484288B1 Statistics signature generation and analysis 有权
标题翻译：统计签名生成和分析
公开(公告)号：US06484288B1
公开(公告)日：2002-11-19
申请号：US09466039
申请日：1999-12-17
申请人： Christopher J. Hall , Robert J. Harrison , Anthony S. Rowell , Amarjit S. Bhandal
发明人： Christopher J. Hall , Robert J. Harrison , Anthony S. Rowell , Amarjit S. Bhandal
IPC分类号： H03M1309
CPC分类号： H03M13/091
摘要： The present invention provides for a statistics Cyclic Redundancy Check (CRC) (108) wherein the statistics CRC (108) is representative of the values contained within a statistics RAM (110). The statistics CRC (108) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.
摘要翻译：本发明提供统计循环冗余校验（CRC）（108），其中统计CRC（108）代表包含在统计RAM（110）内的值。统计CRC（108）然后用于通过读取该签名来确定统计信息的有效性而不是读取所有单个统计信息来减少测试向量。对于每次完整的统计数据，签名将被重新生成，并且该注册表的内容仅在通过完成时更新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式