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1. 发明授权

US06484288B1 Statistics signature generation and analysis 有权
标题翻译：统计签名生成和分析
公开(公告)号：US06484288B1
公开(公告)日：2002-11-19
申请号：US09466039
申请日：1999-12-17
申请人： Christopher J. Hall , Robert J. Harrison , Anthony S. Rowell , Amarjit S. Bhandal
发明人： Christopher J. Hall , Robert J. Harrison , Anthony S. Rowell , Amarjit S. Bhandal
IPC分类号： H03M1309
CPC分类号： H03M13/091
摘要： The present invention provides for a statistics Cyclic Redundancy Check (CRC) (108) wherein the statistics CRC (108) is representative of the values contained within a statistics RAM (110). The statistics CRC (108) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.
摘要翻译：本发明提供统计循环冗余校验（CRC）（108），其中统计CRC（108）代表包含在统计RAM（110）内的值。统计CRC（108）然后用于通过读取该签名来确定统计信息的有效性而不是读取所有单个统计信息来减少测试向量。对于每次完整的统计数据，签名将被重新生成，并且该注册表的内容仅在通过完成时更新。

2. 发明授权

US06606361B1 Circuits, systems, and methods for providing a single output clock and output data stream from an interface having multiple clocks and an input data stream 有权
标题翻译：用于从具有多个时钟的接口和输入数据流提供单个输出时钟和输出数据流的电路，系统和方法
公开(公告)号：US06606361B1
公开(公告)日：2003-08-12
申请号：US09407815
申请日：1999-09-28
申请人： Anthony S. Rowell
发明人： Anthony S. Rowell
IPC分类号： H04L700
CPC分类号： H03K5/1534 , H04L7/0012
摘要： A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal.
摘要翻译：一种用于产生单个输出数据（DOUT）流和相应的单个时钟信号（CLKOUT）的电路（10）。该电路包括用于接收单个输入数据流（DIN）的输入，其中输入数据流具有第一频率的数据字。该电路还包括用于接收多个对应时钟信号（CLK0，CLK1）的多个时钟输入，其中多个对应的时钟信号中的每一个被同步到对应的多个数据字。该电路还包括用于接收快速时钟信号（CLKF）的输入，其中快速时钟信号具有大于第一频率的快速频率。该电路还包括各种电路。该电路包括用于以快速频率采样（L20，L21）输入数据流的电路，用于输出（M，LM）采样数据作为单个输出数据流的电路，以及用于将单个时钟周期输出（CG）的电路响应快速时钟信号。

3. 发明授权

US06519301B1 Circuits, systems, and methods for passing request information across differing clock domains 有权
标题翻译：用于在不同时钟域传递请求信息的电路，系统和方法
公开(公告)号：US06519301B1
公开(公告)日：2003-02-11
申请号：US09406926
申请日：1999-09-28
申请人： Anthony S. Rowell
发明人： Anthony S. Rowell
IPC分类号： H04L700
CPC分类号： H04L7/02
摘要： A system (20) for communicating request information from a first circuit (state machine A) operable according to a first clock domain (CLKA) to a second circuit (state machine B) operable according to a second clock domain (CLKB). In the system, the first clock domain differs from the second clock domain. The system comprises a flag circuit (F2) for storing a flag having a changeable state. The flag circuit comprises an input for receiving a toggle control signal (TOGGLE) and the state of the flag changes in response to assertion of the toggle control signal, where the first circuit is operable to assert the toggle signal to communicate the request information to the second circuit. The system further comprises a synchronizing circuit (SCD) having an input coupled to an output of the flag circuit and for receiving the state of the flag. The system further comprises a detection circuit (ED) having an input coupled to an output of the synchronizing circuit. The detection circuit is operable to detect a change in the state of the flag and to output a detection control signal (P) to the second circuit in response to detection a change in the state of the flag.
摘要翻译：一种用于将可根据第一时钟域（CLKA）操作的第一电路（状态机A）的请求信息传送到根据第二时钟域（CLKB）可操作的第二电路（状态机B）的系统（20）。在系统中，第一个时钟域与第二个时钟域不同。该系统包括用于存储具有可变状态的标志的标志电路（F2）。标志电路包括用于接收切换控制信号（TOGGLE）的输入，并且标志的状态响应于切换控制信号的断言而改变，其中第一电路可操作地断言切换信号以将请求信息传送到第二电路。该系统还包括具有耦合到标志电路的输出并用于接收该标志的状态的输入的同步电路（SCD）。该系统还包括具有耦合到同步电路的输出的输入的检测电路（ED）。检测电路可操作以检测标志的状态的变化，并且响应于检测到标志的状态的改变而将检测控制信号（P）输出到第二电路。

4. 发明授权

US06369670B1 Dynamically adjustable tapped delay line 有权
标题翻译：动态调节抽头延时线
公开(公告)号：US06369670B1
公开(公告)日：2002-04-09
申请号：US09406085
申请日：1999-09-27
申请人： Anthony S. Rowell
发明人： Anthony S. Rowell
IPC分类号： H03H720
CPC分类号： H03K5/135
摘要： A circuit (43) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines (40) are coupled to the signals, each tapped delay line including a plurality of delay elements (42) and having a plurality of exit points (E) through which said signal may propagate. A test circuit (20) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.
摘要翻译：电路（43）产生要延迟相应时间间隔的一个或多个信号。抽头延迟线（40）耦合到信号，每个抽头延迟线包括多个延迟元件（42）并且具有多个出口点（E），所述信号可以通过该出口点传播。测试电路（20）确定与电路中的延迟元件相关联的延迟，并基于所述延迟选择每个所述抽头延迟线的所述出口点之一。

5. 发明授权

US06650654B1 Early preamble transmission 有权
标题翻译：早期前导传输
公开(公告)号：US06650654B1
公开(公告)日：2003-11-18
申请号：US09459282
申请日：1999-12-17
申请人： Sean N. Batty , Anthony S. Rowell
发明人： Sean N. Batty , Anthony S. Rowell
IPC分类号： H04L12413
CPC分类号： H04L49/9089 , H04L12/40013 , H04L49/90 , H04L49/9068
摘要： The present invention is a method of reducing latency in transmitting frames of data in a shared access media environment whereby the preamble of the next frame to be transmitted is transmitted while the data portion of the next frame to be transmitted is being retrieved. In another aspect, the early transmission of the preamble of the next frame is started no later than the time it normally takes to fetch and prepare the next frame for transmission less the time it takes to transmit the preamble.
摘要翻译：本发明是一种减少在共享存取媒体环境中发送数据帧的等待时间的方法，由此在要发送的下一帧的数据部分被检索时发送下一帧的前导码。在另一方面，下一帧的前同步码的早期发送不迟于通常需要的时间开始，并且准备下一个帧进行发送，而不需要传输前导码所需的时间。

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