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1. 发明申请

WO2011064372A2 DOSIMETER POWERED BY PASSIVE RF ABSORPTION 审中-公开
标题翻译：通过无源射频吸收驱动的计量器
公开(公告)号：WO2011064372A2
公开(公告)日：2011-06-03
申请号：PCT/EP2010/068435
申请日：2010-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ROSSNAGEL, Stephen , CABRAL JR, Cyril , MURRAY, Conal, Eugene , WISNIERFF, Robert, Luke , KOESTER, Steven, John , RODBELL, Kenneth, Parker , GORDON, Michael , YAU, Jeng-Bang
发明人： ROSSNAGEL, Stephen , CABRAL JR, Cyril , MURRAY, Conal, Eugene , WISNIERFF, Robert, Luke , KOESTER, Steven, John , RODBELL, Kenneth, Parker , GORDON, Michael , YAU, Jeng-Bang
IPC分类号： G01T1/02
CPC分类号： G01T1/026
摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.
摘要翻译：用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变，剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。

2. 发明申请

WO2011057917A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：WO2011057917A1
公开(公告)日：2011-05-19
申请号：PCT/EP2010/066638
申请日：2010-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NING, Tak, Hung , CAI, Jin , YAU, Jeng-Bang , KHAKIFIROOZ, Ali , DENNARD, Robert, Heath
发明人： NING, Tak, Hung , CAI, Jin , YAU, Jeng-Bang , KHAKIFIROOZ, Ali , DENNARD, Robert, Heath
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means comprise Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

3. 发明申请

WO2011057857A1 ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX 审中-公开
标题翻译：具有超薄SOI和ULTRATHIN BOX的SOI器件的隔离结构
公开(公告)号：WO2011057857A1
公开(公告)日：2011-05-19
申请号：PCT/EP2010/064435
申请日：2010-09-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , KHATER, Marwan , DENNARD, Robert, Heath , YAU, Jeng-Bang , SHI, Leathen
发明人： KHATER, Marwan , DENNARD, Robert, Heath , YAU, Jeng-Bang , SHI, Leathen
IPC分类号： H01L21/762
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

4. 发明申请

WO2011054852A1 HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS 审中-公开
标题翻译：混合双盒返回门式带有增强移动通道的绝缘硅绝缘子
公开(公告)号：WO2011054852A1
公开(公告)日：2011-05-12
申请号：PCT/EP2010/066715
申请日：2010-11-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , OUYANG, Qiqing, Christine , DENNARD, Robert, Heath , YAU, Jeng-Bang
发明人： OUYANG, Qiqing, Christine , DENNARD, Robert, Heath , YAU, Jeng-Bang
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L21/336 , H01L29/786
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.
摘要翻译：用于集成电路器件的半导体晶片结构包括块状衬底; 形成在本体基板上的下绝缘层; 形成在下绝缘层上的导电背栅层; 形成在所述背栅层上的上绝缘层; 以及形成在所述上绝缘层上的混合半导体绝缘体层，所述混合半导体绝缘体层包括具有第一晶体取向的第一部分和具有第二晶体取向的第二部分。

5. 发明申请

WO2012096914A1 RADIATION HARDENED TRANSISTORS BASED ON GRAPHENE AND CARBON NANOTUBES 审中-公开
标题翻译：基于石墨和碳纳米管的辐射硬化晶体管
公开(公告)号：WO2012096914A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/020713
申请日：2012-01-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LIN, Yu-Ming , YAU, Jeng-Bang
发明人： LIN, Yu-Ming , YAU, Jeng-Bang
IPC分类号： H01L51/10 , H01L51/30
CPC分类号： H01L29/16 , H01L21/02378 , H01L21/02381 , H01L21/0242 , H01L21/02488 , H01L21/02527 , H01L21/02656 , H01L29/1606 , H01L29/66742 , H01L29/78603 , H01L29/78684
摘要： Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.
摘要翻译：提供了基于石墨烯和/或碳纳米管的辐射 - 硬晶体管器件及其制造技术。一方面，提供一种制造辐射 - 硬质晶体管的方法。该方法包括以下步骤。提供辐射硬质基板。碳基材料形成在基板上，其中一部分碳基材料用作晶体管的沟道区，碳基材料的其它部分用作晶体管的源极和漏极区。触点形成为用作晶体管的源区和漏区的碳基材料的部分。在用作晶体管的沟道区的碳基材料的部分上沉积栅极电介质。在栅极电介质上形成顶栅接触。

6. 发明申请

WO2021018466A1 SYSTEM AND METHOD FOR FORMING SOLDER BUMPS 审中-公开
公开(公告)号：WO2021018466A1
公开(公告)日：2021-02-04
申请号：PCT/EP2020/066803
申请日：2020-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： LEWANDOWSKI, Eric, Peter , NAH, Jae-Woong , YAU, Jeng-Bang , SORCE, Peter, Jerome
IPC分类号： H01L21/60 , H01L23/485 , H01L23/498 , H01L27/18
摘要： A method for forming a solder bump (122) includes preparing a transfer mold (100) having a solder pillar (112) extending from a mold substrate (102) and through a first photoresist layer (104) and having a shape partially defined by a second photoresist layer (108) that is removed prior to transfer of the solder; providing a device substrate (114) having a wettable pad (120); placing the transfer mold (100) and the device substrate (114) into aligned contact such that the solder pillar (112) is in contact with the wettable pad (120); forming a metallic bond between the solder pillar (112) and the wettable pad (120), e.g. by a cold welding process or a reflow process; and removing the mold substrate (102) and the first photoresist layer (104). The mold substrate (102) and the transfer mold (100) may be flexible. The transfer mold may comprise at least one of: a wetting layer over the mold substrate (402), in which case a pillar (112) including aluminum may be deposited and reflowed; a seed layer over the mold substrate (402); and a non-wetting layer over the second photoresist layer (408). The device substrate (114, 502) may comprise a through hole (118, 504) and may be an interposer made of silicon, glass and/or organic substrate material. The method may further comprise attaching the interposer (114, 502) to a qubit semiconductor device (a superconducting chip) (300, 516), wherein the qubit semiconductor device (300, 516) comprises a Josephson junction (304, 518), and wherein the attaching of the interposer (114, 502) to the qubit semiconductor device (300, 516) includes aligning the hole (118, 504) through the interposer (114, 502) with the Josephson junction (304, 518) to provide a path for accessing the Josephson junction (304, 518), in particular to make adjustments to its design frequency. The solder pillar (122) may be one of a plurality of solder pillars that are formed around the hole (118) between the qubit semiconductor device (300) and the interposer (114) for providing an amount of thermal isolation of the Josephson junction (304), forming a circular wall (200A, 200B) around the qubits and between the interposer (114) and the superconducting chip (300), wherein the circular wall (200A, 200B) may include at least one gap (202) therethrough. The solder pillar (512) may be one of a plurality of solder pillars (512) of the transfer mold, including a first solder pillar (512) having a first diameter and a second solder pillar (512) having a second diameter, the first diameter being larger than the second diameter. The device substrate (602) may comprise a semiconductor substrate comprising a deep recess (604), wherein a circuit component (608) may be comprised in the deep recess (604). The preparing of the transfer mold (100) may comprise: patterning the first and second photoresist layers (104, 108) to define a recess (110) that extends through the first and second photoresist layers (104, 108); and using injection molded soldering (IMS) to fill the recess (110) with solder to form the solder pillar (112). Alternatively, the preparing of the transfer mold may comprise: patterning the first and second photoresist layers (404, 408) to define a recess (410) that extends through the first and second photoresist layers (404, 408); forming a seed layer, wherein at least a portion of the seed layer is provided in the recess (410); and using electroplating to fill the recess (410) with solder and form the solder pillar. The pillars (112) may also be 3-D metal posts formed by copper plating or copper stud bumps.

7. 发明申请

WO2021259712A1 SELECTIVE CHEMICAL FREQUENCY MODIFICATION OF JOSEPHSON JUNCTION RESONATORS 审中-公开
公开(公告)号：WO2021259712A1
公开(公告)日：2021-12-30
申请号：PCT/EP2021/066160
申请日：2021-06-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： LEWANDOWSKI, Eric , YAU, Jeng-Bang , ZHANG, Eric , WEBB, Bucknell
IPC分类号： H01L39/24 , H01L27/18 , G06N10/00 , G06N10/40 , H01L39/223 , H01L39/2493
摘要： Techniques for selectively tuning the operating frequency of superconducting Josephson junction resonators are provided which include chemically altering a Josephson junction (110) via a plasma treatment, preferably by masked exposure of a transmon qubit die (104) to plasma (502) including reactants such as hydrogen or oxygen. In particular, the plasma treatment adjusts an electrical resistance of the Josephson junction. An apparatus for carrying out the plasma treatment is also disclosed.

8. 发明公开

EP4173055A1 SELECTIVE CHEMICAL FREQUENCY MODIFICATION OF JOSEPHSON JUNCTION RESONATORS 审中-实审
公开(公告)号：EP4173055A1
公开(公告)日：2023-05-03
申请号：EP21734312.8
申请日：2021-06-15
申请人： International Business Machines Corporation
发明人： LEWANDOWSKI, Eric , YAU, Jeng-Bang , ZHANG, Eric , WEBB, Bucknell
IPC分类号： H01L39/24 , H01L27/18 , G06N10/00

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