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1. 发明申请

WO2022269447A1 STACKED FET WITH DIFFERENT CHANNEL MATERIALS 审中-公开
公开(公告)号：WO2022269447A1
公开(公告)日：2022-12-29
申请号：PCT/IB2022/055686
申请日：2022-06-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： XIE, Ruilong , MILLER, Eric , GUO, Dechao , SHEARER, Jeffrey , FAN, Su Chen , FROUGIER, Julien , BASKER, Veeraraghavan , WANG, Junli , SUK, Sung Dae
IPC分类号： H01L27/088 , H01L21/336 , H01L21/02532 , H01L21/0259 , H01L21/02609 , H01L21/823807 , H01L27/0922 , H01L29/045 , H01L29/0665 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/775 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

2. 发明申请

WO2023072792A1 INTEGRATING STANDARD-GATE TRANSISTORS AND EXTENDED-GATE TRANSISTORS ON THE SAME SUBSTRATE USING LOW-TEMPERATURE GATE DIELECTRIC TREATMENTS 审中-公开
公开(公告)号：WO2023072792A1
公开(公告)日：2023-05-04
申请号：PCT/EP2022/079504
申请日：2022-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： BAO, Ruqiang , WANG, Junli , GUO, Dechao
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/775
摘要： Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form an extended-gate field effect transistor (EG-FET) on a substrate (102). The fabrication operations include forming a channel in an EG region of the substrate. A first EG gate dielectric (702) is deposited over the channel at a first low-temperature. A reinforcement treatment is applied to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric (702A). The first low-temperature is selected to be below the second low-temperature; and the second low-temperature is selected to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level or rate.

3. 发明申请

WO2023089469A1 NANOSHEET REPLACEMENT DUAL METAL GATE PATTERNING SCHEME 审中-公开
公开(公告)号：WO2023089469A1
公开(公告)日：2023-05-25
申请号：PCT/IB2022/060930
申请日：2022-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： BAO, Ruqiang , GUO, Jing , WANG, Junli , GUO, Dechao
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/775
摘要： A device includes a base layer structure (705) including a first region and a second region; a first bottom gate material (704) in a plurality of first-type doped (e. g. nFET) regions in the first and second regions; a second bottom gate material (706) in a second-type doped (e.g. pFET) regions in the first and second regions; first nanosheet gate-all-round device structures (702, 703) on the first bottom gate material; and second nanosheet gate-all-round device structures on the second bottom gate material, wherein the first bottom gate material is located over the second nanosheet gate-all-around device structures in the second-type doped regions of the first and second regions, wherein the second bottom gate material extends, in boundary regions between the first-type and second-type doped regions, on the base layer structure from the second nanosheet gate-all-around devices structures toward the first gate-all-round device structures.

4. 发明申请

WO2022008295A1 STACKED GATE STRUCTURES 审中-公开
公开(公告)号：WO2022008295A1
公开(公告)日：2022-01-13
申请号：PCT/EP2021/067830
申请日：2021-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： ZHANG, Chen , GUO, Dechao , WANG, Junli , XIE, Ruilong , CHENG, Kangguo , LI, Juntao , PARK, Chanro , BAO, Ruqiang , SUK, Sung Dae , YU, Lan , WU, Heng
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66
摘要： An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

5. 发明申请

WO2023083699A1 GATE-CUT AND SEPARATION TECHNIQUES FOR ENABLING INDEPENDENT GATE CONTROL OF STACKED TRANSISTORS 审中-公开
公开(公告)号：WO2023083699A1
公开(公告)日：2023-05-19
申请号：PCT/EP2022/080746
申请日：2022-11-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： XIE, Ruilong , LOUBET, Nicolas , FROUGIER, Julien , CLEVENGER, Lawrence , BHOSALE, Prasad , WANG, Junli , PRANATHARTHIHARAN, Balasubramanian , GUO, Dechao
IPC分类号： H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/06 , H01L29/775
摘要： Vertically stacked field-effect transistors (FETs) with independent and shared gates are disclosed. The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

6. 发明申请

WO2023035747A1 HYBRID COMPLEMENTARY FIELD EFFECT TRANSISTOR DEVICE 审中-公开
公开(公告)号：WO2023035747A1
公开(公告)日：2023-03-16
申请号：PCT/CN2022/103647
申请日：2022-07-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： XIE, Ruilong , ZHANG, Chen , ZHANG, Jingyun , WANG, Junli , MONTANINI, Pietro
IPC分类号： H01L21/8232 , H01L27/085
摘要： A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

7. 发明申请

WO2023045484A1 BURIED CONTACT THROUGH FIN-TO-FIN SPACE FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：WO2023045484A1
公开(公告)日：2023-03-30
申请号：PCT/CN2022/103768
申请日：2022-07-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： WANG, Junli , ANDERSON, Brent
IPC分类号： H01L21/8234 , H01L29/417
摘要： Fabrication methods and resulting structures are disclosed to provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. A buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.

8. 发明申请

WO2021053419A1 TRAPEZOIDAL INTERCONNECT AT TIGHT BEOL PITCH 审中-公开
公开(公告)号：WO2021053419A1
公开(公告)日：2021-03-25
申请号：PCT/IB2020/057667
申请日：2020-08-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： LANZILLO, Nicholas, Anthony , SHOBHA, Hosadurga , HUANG, Huai , WANG, Junli , MOTOYAMA, Koichi , PENNY, Christopher , CLEVENGER, Lawrence
IPC分类号： H01L21/768
摘要： Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

9. 发明申请

WO2016110793A1 BOTTOM-UP METAL GATE FORMATION ON REPLACEMENT METAL GATE FINFET DEVICES 审中-公开
标题翻译：底部金属门形成替代金属栅极FinFET器件
公开(公告)号：WO2016110793A1
公开(公告)日：2016-07-14
申请号：PCT/IB2016/050022
申请日：2016-01-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： HONG, He , WANG, Junli , YANG, Chih-Chao , LI, Juntao
IPC分类号： H01L21/28
CPC分类号： H01L29/6681 , H01L21/28079 , H01L21/28088 , H01L21/32139 , H01L29/7851
摘要： A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and a method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure (140) over a substrate (110), the dummy gate structure (140) being surrounded by an insulating layer (120), and removing the dummy gate structure (140) so as to expose a trench (121) within the insulating layer (120). The method also includes conformally depositing a dielectric material layer (160) and a work function metal layer (170) over the insulating layer (120) and in the trench (121) and removing the dielectric material layer (160) and the work function metal layer (170) from a tip surface of the insulating layer (120), recessing the work function metal layer (170) below a top of the trench (121), and selectively forming a gate metal (190) only on exposed surfaces of the work function metal layer (170).
摘要翻译：描述了在晶体管器件中制造替换金属栅极的方法，鳍状场效应晶体管（finFET）以及用替换金属栅极制造finFET器件的方法。制造替代金属栅极的方法包括在衬底（110）上形成虚拟栅极结构（140），所述虚拟栅极结构（140）由绝缘层（120）围绕，并且去除所述虚拟栅极结构（140）以便露出绝缘层（120）内的沟槽（121）。该方法还包括在绝缘层（120）上和沟槽（121）中共形沉积介电材料层（160）和功函数金属层（170），并去除介电材料层（160）和功函数金属层（170）从绝缘层（120）的尖端表面，将功函数金属层（170）凹入到沟槽（121）的顶部之下，并且仅在所述沟槽（121）的暴露表面上选择性地形成栅极金属（190）功能金属层（170）。

10. 发明申请

WO2023045609A1 THREE-DIMENSIONAL, MONOLITHICALLY STACKED FIELD EFFECT TRANSISTORS FORMED ON FRONTSIDE AND BACKSIDE OF WAFER 审中-公开
公开(公告)号：WO2023045609A1
公开(公告)日：2023-03-30
申请号：PCT/CN2022/111724
申请日：2022-08-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： SUK, Sung Dae , GHOSH, Somnath , ZHANG, Chen , WANG, Junli , SADANA, Devendra K. , GUO, Dechao
IPC分类号： H01L21/822 , H01L29/06
摘要： A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

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