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1. 发明申请

WO2007084982A3 DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE 审中-公开
公开(公告)号：WO2007084982A3
公开(公告)日：2007-07-26
申请号：PCT/US2007/060767
申请日：2007-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , DOWNES, Keith, E. , LINDGREN, Peter, J. , STAMPER, Anthony, K.
发明人： COOLBAUGH, Douglas, D. , DOWNES, Keith, E. , LINDGREN, Peter, J. , STAMPER, Anthony, K.
IPC分类号： H01L23/48
摘要： A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).

2. 发明申请

WO2011090852A3 THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
公开(公告)号：WO2011090852A3
公开(公告)日：2011-07-28
申请号：PCT/US2011/020913
申请日：2011-01-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HERRIN, Russell, T. , LINDGREN, Peter, J. , SPROGIS, Edmund, J. , STAMPER, Anthony, K.
发明人： HERRIN, Russell, T. , LINDGREN, Peter, J. , SPROGIS, Edmund, J. , STAMPER, Anthony, K.
IPC分类号： H01L21/768
摘要： A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

3. 发明申请

WO2010017062A1 METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
标题翻译：通过基板VIAS集成的金属接线结构
公开(公告)号：WO2010017062A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051908
申请日：2009-07-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COLLINS, David, S. , JOSEPH, Alvin , LINDGREN, Peter, J. , STAMPER, Anthony, K. , WATSON, Kimball, M.
发明人： COLLINS, David, S. , JOSEPH, Alvin , LINDGREN, Peter, J. , STAMPER, Anthony, K. , WATSON, Kimball, M.
IPC分类号： H01L23/522
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) (20) is formed through a semiconductor substrate (12) and a contact- via-level dielectric layer (50) thereupon. A metal-wire-level dielectric layer (60) and a line-level metal wiring structure (80) embedded therein are formed directly on the contact-via-level dielectric layer (50). The line-level metal wiring structure (80) includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer (60). In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs (20) to maximize the contact area between the TSVs (20) and the line-level metal wiring structure (80). In another embodiment, a set of cheesing holes overlying an entirety of seams (18) in the array of TSVs (20) is formed to prevent trapping of any plating solution in the seams (19)of the TSVs (20) during plating to prevent corrosion of the TSVs (20)at the seams (19).
摘要翻译：穿过衬底通孔（TSV）（20）的阵列通过半导体衬底（12）和接触通过级介电层（50）在其上形成。直接在接触通路层电介质层（50）上形成金属线层介电层（60）和嵌入其中的线状金属布线结构（80）。线状金属布线结构（80）包括填充有金属线层介电层（60）的隔离部分的奶酪孔。在一个实施例中，整个烘干孔位于TSV（20）阵列的区域的外侧，以最大化TSV（20）和线路级金属布线结构（80）之间的接触面积。在另一个实施例中，形成了覆盖在TSV（20）阵列中的整个接缝（18）的一组烘干孔，以防止在电镀期间捕获TSV（20）的接缝（19）中的任何电镀溶液以防止接缝处的TSV（20）的腐蚀（19）。

4. 发明申请

WO2009102741A1 THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 审中-公开
标题翻译：通过包括插入式灌装机在内的基板
公开(公告)号：WO2009102741A1
公开(公告)日：2009-08-20
申请号：PCT/US2009/033723
申请日：2009-02-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LINDGREN, Peter, J. , SPROGIS, Edmund, J. , STAMPER, Anthony, K. , STEIN, Kenneth, J.
发明人： LINDGREN, Peter, J. , SPROGIS, Edmund, J. , STAMPER, Anthony, K. , STEIN, Kenneth, J.
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through substrate (10) via includes an annular conductor layer at a periphery of a through substrate (10) aperture, and a plug layer (24) surrounded by the annular conductor layer. A method for fabricating the through substrate (10) via includes forming a blind aperture within a substrate (10) and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer (20) that does not fill the aperture and plug layer (24) that does fill the aperture. The backside of the substrate (10) may then be planarized to expose at least the planarized conformal conductor layer. (20)
摘要翻译：贯穿基板（10）通孔包括在通孔基板（10）的周边的环形导体层和由环形导体层包围的插塞层（24）。一种用于制造穿透基底（10）通孔的方法，包括在基底（10）内形成盲孔，并且在盲孔内依次形成并随后在盲孔内平坦化形成不填充孔径和塞子层（24）的共形导体层（20）），其中填充了孔径。然后可以将衬底（10）的背面平坦化以至少露出平坦化的共形导体层。（20）

5. 发明申请

WO2008091923A2 REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
标题翻译：在半导体制造中去除蚀刻工艺残留
公开(公告)号：WO2008091923A2
公开(公告)日：2008-07-31
申请号：PCT/US2008/051758
申请日：2008-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HERRIN, Russell, T. , LINDGREN, Peter, J. , STAMPER, Anthony, K.
发明人： HERRIN, Russell, T. , LINDGREN, Peter, J. , STAMPER, Anthony, K.
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5223 , H01L21/02063 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.
摘要翻译：半导体结构及其形成方法。半导体制造方法包括提供结构的步骤。一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域，介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

6. 发明申请

WO2009120587A1 INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE AND RELATED METHOD 审中-公开
标题翻译：具有导电线中开放的电感器及相关方法
公开(公告)号：WO2009120587A1
公开(公告)日：2009-10-01
申请号：PCT/US2009/037738
申请日：2009-03-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ERTURK, Mete , GILLIS, John, D. , GRANT, Casey, J. , SCAGNELLI, David , STAMPER, Anthony, K.
发明人： ERTURK, Mete , GILLIS, John, D. , GRANT, Casey, J. , SCAGNELLI, David , STAMPER, Anthony, K.
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments of an inductor (100) including a conductive line (102 A, 102B) including at least one turn (104) and an opening (106) positioned within an interior of a region (122) of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
摘要翻译：公开了一种包括导线（102A，102B）的电感器（100）的实施例，该导线包括位于导线的区域（122）内部的至少一个匝（104）和开口（106）。还公开了设计电感器的相关方法的实施例。

7. 发明申请

WO2013012544A1 SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING 审中-公开
标题翻译：具有平面屏障层的SAW滤波器及其制造方法
公开(公告)号：WO2013012544A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/044908
申请日：2012-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ADKISSON, James, W. , CANDRA, Panglijen , DUNBAR, Thomas, J. , GAMBINO, Jeffrey, P. , JAFFE, Mark, D. , STAMPER, Anthony, K. , WOLF, Randy, L.
发明人： ADKISSON, James, W. , CANDRA, Panglijen , DUNBAR, Thomas, J. , GAMBINO, Jeffrey, P. , JAFFE, Mark, D. , STAMPER, Anthony, K. , WOLF, Randy, L.
IPC分类号： H03H9/64
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate (110; Fig 3); a planar barrier layer (120) disposed above the piezoelectric substrate, and at least one conductor buried (130) in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片（110;图3）; 设置在所述压电基板上方的平面阻挡层（120），以及在所述压电基板和所述平面阻挡层中埋设的至少一个导体（130）。

8. 发明申请

WO2012177304A2 MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：微电子机械系统（MEMS）及相关执行机构的制造，制造和设计结构的方法
公开(公告)号：WO2012177304A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/029005
申请日：2012-03-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JAHNES, Christopher, V. , STAMPER, Anthony, K.
发明人： JAHNES, Christopher, V. , STAMPER, Anthony, K.
IPC分类号： H02N1/00 , H05K13/00
CPC分类号： H01H59/0009 , B81B3/001 , B81B7/0006 , B81B2201/016 , B81B2203/0118 , B81B2203/04 , B81C1/0015 , B81C1/00293 , B81C2203/0145 , G06F17/5045 , G06F17/5068 , H01H1/0036 , H01H2001/0057 , Y10T29/49121
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.
摘要翻译：提供微机电系统（MEMS）结构，制造方法和设计结构。形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被确定为防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。致动器电极阵列形成为与MEMS光束的下侧和固定致动器电极的表面中的至少一个直接接触。

9. 发明申请

WO2007115146A2 PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
标题翻译：在混合方向晶体管中对充电损害的保护
公开(公告)号：WO2007115146A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/065604
申请日：2007-03-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HOOK, Terence, B. , MOCUTA, Anda, C. , SLEIGHT, Jeffrey, W. , STAMPER, Anthony, K.
发明人： HOOK, Terence, B. , MOCUTA, Anda, C. , SLEIGHT, Jeffrey, W. , STAMPER, Anthony, K.
IPC分类号： A61K31/203 , A61K9/127
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
摘要翻译：芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下伏体区域（18）导通连通，第一区域（24）和本体区域（20）具有第一晶体取向。 SOI器件（10）设置在通过掩埋介电层（16）与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向第一个晶体取向。在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。或者，体器件可以包括NFET，并且SOI器件可以包括PFET。当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管地区。当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

10. 发明申请

WO2005117085A2 METHOD AND FORMING A SEMICONDUCTOR DEVICE HAVING AIR GAPS AND THE STRUCTURE SO FORMED 审中-公开
标题翻译：方法和形成具有空气GAPS和形成的结构的半导体器件
公开(公告)号：WO2005117085A2
公开(公告)日：2005-12-08
申请号：PCT/US2005/018050
申请日：2005-05-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION? , STAMPER, Anthony, K.
发明人： STAMPER, Anthony, K.
IPC分类号： H01L21/311
CPC分类号： H01L21/7682 , H01L21/31116 , H01L21/76807 , H01L28/87
摘要： A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.
摘要翻译：形成半导体器件的方法和如此形成的器件。沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。在电介质材料的交替层内形成第一特征（22,24）。选择性地蚀刻介电材料的交替层以去除具有第一介电材料的每个层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

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