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1. 发明申请

US20150364362A1 WAFER STRESS CONTROL WITH BACKSIDE PATTERNING 有权
标题翻译：具有背面图案的波浪压力控制
公开(公告)号：US20150364362A1
公开(公告)日：2015-12-17
申请号：US14306598
申请日：2014-06-17
申请人： International Business Machines Corporation
发明人： Edward Engbrecht , Donghun Kang , Rishikesh Krishnan , Oh-jung Kwon , Karen A. Nummy
IPC分类号： H01L21/762 , H01L21/66 , H01L29/06 , H01L21/308 , H01L21/321
CPC分类号： H01L21/76227 , H01L21/302 , H01L21/308 , H01L21/3081 , H01L21/3212 , H01L22/12 , H01L29/0603 , H01L29/945
摘要： Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
摘要翻译：本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片正面上的电功能DT。在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

2. 发明授权

US10204823B2 Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing 有权
公开(公告)号：US10204823B2
公开(公告)日：2019-02-12
申请号：US15857042
申请日：2017-12-28
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
IPC分类号： H01L21/70 , H01L29/66 , H01L21/762 , H01L21/324
摘要： A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

3. 发明申请

US20170033001A1 ENHANCING ROBUSTNESS OF SOI SUBSTRATE CONTAINING A BURIED N+ SILICON LAYER FOR CMOS PROCESSING 有权
标题翻译：增强包含用于CMOS处理的B + N +硅层的SOI衬底的稳定性
公开(公告)号：US20170033001A1
公开(公告)日：2017-02-02
申请号：US14815314
申请日：2015-07-31
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
IPC分类号： H01L21/762 , H01L21/324
CPC分类号： H01L21/76251 , H01L21/324
摘要： A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
摘要翻译：在n +硅层和SOI衬底的氧化物层之间提供选自未掺杂硅，p掺杂硅或多层堆叠的硅缓冲层，以任意顺序，未掺杂的硅和p掺杂的硅。在需要电场的器件处理期间，硅缓冲层的存在减少了到氧化物层的电子注入。

4. 发明授权

US09029862B2 Low resistance embedded strap for a trench capacitor 有权
标题翻译：用于沟槽电容器的低电阻嵌入式带
公开(公告)号：US09029862B2
公开(公告)日：2015-05-12
申请号：US13901802
申请日：2013-05-24
申请人： International Business Machines Corporation
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L21/48 , H01L29/66 , H01L27/108 , H01L29/94 , H01L21/82
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.
摘要翻译：在半导体衬底中形成沟槽，并且填充有节点电介质层和用作内部电极的至少一个导电材料填充部分。所述至少一个导电材料填充部分包括掺杂多晶半导体填充部分。在半导体衬底上形成用于存取晶体管的栅极堆叠，并且在栅叠层周围形成栅极间隔物。源极/漏极沟槽形成在栅极间隔物的外侧壁和掺杂多晶半导体填充部分的侧壁之间。通过选择性外延工艺同时形成外延源极区域和多晶半导体材料部分，使得外延源极区域和多晶半导体材料部分彼此接触而没有间隙。多晶半导体材料部分在源极区域和内部电极之间提供鲁棒的低电阻导电路径。

5. 发明申请

US20180122688A1 ENHANCING ROBUSTNESS OF SOI SUBSTRATE CONTAINING A BURIED N+ SILICON LAYER FOR CMOS PROCESSING 审中-公开
公开(公告)号：US20180122688A1
公开(公告)日：2018-05-03
申请号：US15857042
申请日：2017-12-28
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
IPC分类号： H01L21/762 , H01L21/324
CPC分类号： H01L21/76251 , H01L21/324
摘要： A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

6. 发明授权

US09257433B2 Structure and method of forming enhanced array device isolation for implanted plate EDRAM 有权
公开(公告)号：US09257433B2
公开(公告)日：2016-02-09
申请号：US14736695
申请日：2015-06-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

7. 发明申请

US20140213053A1 SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD 有权
标题翻译：包括基板接触的半导体器件和相关方法
公开(公告)号：US20140213053A1
公开(公告)日：2014-07-31
申请号：US13749830
申请日：2013-01-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Karen A. Nummy , Ravi M. Todi
IPC分类号： H01L21/02
CPC分类号： H01L21/743 , H01L29/945
摘要： A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.
摘要翻译：公开了一种在半导体器件上形成接触的方法。所述方法包括：在所述半导体器件上形成掩模，所述掩模暴露设置在所述半导体器件的衬底中的沟槽内的至少一个接触节点; 在所述半导体器件上执行第一衬底接触蚀刻，所述第一衬底接触蚀刻凹陷所述沟槽内的所述暴露的接触节点; 去除设置在暴露的接触节点之上和沟槽的侧面上的一组节点膜; 以及在所述暴露的接触节点之上的所述沟槽内形成接触区域，所述接触区域接触所述衬底。

8. 发明申请

US20130260520A1 LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR 有权
标题翻译：用于电容电容器的低电阻嵌入式带
公开(公告)号：US20130260520A1
公开(公告)日：2013-10-03
申请号：US13901802
申请日：2013-05-24
申请人： International Business Machines Corporation
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L21/48 , H01L21/82
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.
摘要翻译：在半导体衬底中形成沟槽，并且填充有节点电介质层和用作内部电极的至少一个导电材料填充部分。所述至少一个导电材料填充部分包括掺杂多晶半导体填充部分。在半导体衬底上形成用于存取晶体管的栅极堆叠，并且在栅叠层周围形成栅极间隔物。源极/漏极沟槽形成在栅极间隔物的外侧壁和掺杂多晶半导体填充部分的侧壁之间。通过选择性外延工艺同时形成外延源极区域和多晶半导体材料部分，使得外延源极区域和多晶半导体材料部分彼此接触而没有间隙。多晶半导体材料部分在源极区域和内部电极之间提供鲁棒的低电阻导电路径。

9. 发明授权

US09922866B2 Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing 有权
公开(公告)号：US09922866B2
公开(公告)日：2018-03-20
申请号：US14815314
申请日：2015-07-31
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
IPC分类号： H01L21/70 , H01L29/66 , H01L21/762 , H01L21/324
CPC分类号： H01L21/76251 , H01L21/324
摘要： A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

10. 发明申请

US20150349121A1 ASYMMETRIC STRESSOR DRAM 有权
标题翻译：不对称压力DRAM
公开(公告)号：US20150349121A1
公开(公告)日：2015-12-03
申请号：US14476897
申请日：2014-09-04
申请人： International Business Machines Corporation
发明人： Ravi K. Dasaka , Shreesh Narasimha , Ahmed Nayaz Noemaun , Karen A. Nummy , Katsunori Onishi , Paul C. Parries , Chengwen Pei , Geng Wang , Bidan Zhang
IPC分类号： H01L29/78 , H01L27/108
CPC分类号： H01L29/7848 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10867 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/66659
摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.
摘要翻译：在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。存取晶体管的体电位与漏极电压的耦合比源电压更强。栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平面化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

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