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1. 发明申请

US20230080397A1 SILICON ON SAPPHIRE SUBSTRATE FOR EDGE COMPUTER 有权
公开(公告)号：US20230080397A1
公开(公告)日：2023-03-16
申请号：US17477520
申请日：2021-09-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Devendra K. Sadana , Ning Li
IPC分类号： H01L25/16 , H01L23/66
摘要： A computing device is provided. The computing device includes a sapphire substrate having a first surface and a second surface opposed to the first surface, a light receiving device having a first surface and a second surface opposed to the first surface, the second surface of the light receiving device coupled to the first surface of the sapphire substrate, a memory coupled to the first surface of the light receiving device, and an antenna coupled to the first surface of the sapphire substrate.

2. 发明授权

US11581472B2 Superconductor-semiconductor Josephson junction 有权
公开(公告)号：US11581472B2
公开(公告)日：2023-02-14
申请号：US16534882
申请日：2019-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Devendra K. Sadana , Ning Li , Stephen W. Bedell , Sean Hart , Patryk Gumann
IPC分类号： H01L39/02 , G06N10/00 , H01L39/22
摘要： A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

3. 发明授权

US11522116B2 Vertical AL/EPI SI/AL, and also AL/AL oxide/AL, josephson junction devices for qubits 有权
公开(公告)号：US11522116B2
公开(公告)日：2022-12-06
申请号：US16847277
申请日：2020-04-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Steven J. Holmes , Devendra K. Sadana
IPC分类号： H01L39/22 , H01L39/24 , H01L39/02
摘要： A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.

4. 发明授权

US11444215B2 Double layered transparent conductive oxide for reduced Schottky barrier in photovoltaic devices 有权
公开(公告)号：US11444215B2
公开(公告)日：2022-09-13
申请号：US16741142
申请日：2020-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , Bay Zu Precision Co., LTD.
发明人： Shun-Ming Chen , Chien-Chih Huang , Joel P. Desouza , Augustin J. Hong , Jeehwan Kim , Chien-Yeh Ku , Devendra K. Sadana , Chuan-Wen Wang
IPC分类号： H01L31/0224 , H01L31/0392 , H01L31/075 , H01L31/18
摘要： A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.

5. 发明授权

US11355703B2 Phase change device with interfacing first and second semiconductor layers 有权
公开(公告)号：US11355703B2
公开(公告)日：2022-06-07
申请号：US16903245
申请日：2020-06-16
申请人： International Business Machines Corporation
发明人： Ning Li , Devendra K. Sadana
IPC分类号： H01L45/00 , G11C13/00
摘要： According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, in some embodiments, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.

6. 发明授权

US11335899B2 Lithium ion energy storage device containing a vapor deposited iodine interfacial layer 有权
公开(公告)号：US11335899B2
公开(公告)日：2022-05-17
申请号：US16397580
申请日：2019-04-29
申请人： International Business Machines Corporation
发明人： John Collins , Ali Afzali-Ardakani , Joel P. de Souza , Teodor K. Todorov , Devendra K. Sadana
IPC分类号： H01M4/133 , H01M4/136 , H01M10/0565 , H01M4/66 , C08K3/04 , C08K5/00 , H01M10/0525 , H01M4/02
摘要： A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.

7. 发明授权

US11322787B2 Encapsulating in-situ energy storage device with cathode contact 有权
公开(公告)号：US11322787B2
公开(公告)日：2022-05-03
申请号：US16687607
申请日：2019-11-18
申请人： International Business Machines Corporation
发明人： John Collins , John M. Papalia , Devendra K. Sadana , Matthew Sagianis
IPC分类号： H01M6/40 , H01M50/10 , H01M10/052 , H01M10/04 , H01M10/02 , H01M10/0565 , H01M10/0585
摘要： An energy storage device has all components, e.g. anode, electrolyte, and cathode contained and sealed with a trench in a substrate. Various methods and structures are disclosed for sealing the components. In some embodiments, a sealer or sealing layer seals the components. One embodiment uses a tension clamp to contain the components with additional pressure. Another embodiment uses a cathode structure cup which is held in place in the substrate via sidewall trench features. Different external connections to the device are disclosed. The invention enables full three-dimensional components to be created and contained entirely within the substrate during assembly, curing, galvanic cycling and other manufacturing processes and provides improved sealing of the components during device operation.

8. 发明授权

US11316022B2 Ion implant defined nanorod in a suspended Majorana fermion device 有权
公开(公告)号：US11316022B2
公开(公告)日：2022-04-26
申请号：US16688386
申请日：2019-11-19
申请人： International Business Machines Corporation
发明人： Steven J. Holmes , Devendra K. Sadana , Sean Hart , Patryk Gumann , Stephen W. Bedell , Ning Li
IPC分类号： H01L29/41 , G06N10/00 , B82Y10/00 , B82Y40/00 , H01L29/06 , H01L39/10 , H01L39/24
摘要： Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.

9. 发明授权

US11309585B2 Molten ion conductive salt/silicon interface for decreased interfacial resistance 有权
公开(公告)号：US11309585B2
公开(公告)日：2022-04-19
申请号：US16389069
申请日：2019-04-19
申请人： International Business Machines Corporation
发明人： John Collins , Ali Afzali-Ardakani , Teodor K. Todorov , Joel P. de Souza , Devendra K. Sadana
IPC分类号： H01M10/39 , H01M10/0562 , H01M10/0525 , H01M4/137 , H01M4/1399 , H01M4/1395 , H01M4/38 , H01M4/131 , H01M4/134 , H01M4/36
摘要： An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

10. 发明申请

US20220102626A1 PHASE-CHANGE MEMORY (PCM) INCLUDING LINER REDUCING RESISTANCE DRIFT 有权
公开(公告)号：US20220102626A1
公开(公告)日：2022-03-31
申请号：US17034057
申请日：2020-09-28
申请人： International Business Machines Corporation
发明人： Ning Li , Joel P. de Souza , Kevin W. Brew , Devendra K. Sadana
IPC分类号： H01L45/00 , H01L27/24
摘要： A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.

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