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1. 发明申请

US20180165094A1 BRANCH PREDICTOR SEARCH QUALIFICATION USING STREAM LENGTH PREDICTION 审中-公开
公开(公告)号：US20180165094A1
公开(公告)日：2018-06-14
申请号：US15376847
申请日：2016-12-13
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Michael J. Cadigan, Jr. , Adam B. Collura , Daniel Lipetz
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3848
摘要： A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.

2. 发明授权

US09606927B2 Set selection of a set-associative storage container 有权
公开(公告)号：US09606927B2
公开(公告)日：2017-03-28
申请号：US15249796
申请日：2016-08-29
申请人： International Business Machines Corporation
发明人： Steven R. Carlough , Adam B. Collura
IPC分类号： G06F12/08 , G06F12/0864
CPC分类号： G06F12/0864 , G06F12/0822 , G06F12/121 , G06F12/122 , G06F12/128 , G06F2212/1044 , G06F2212/601 , G06F2212/6032 , G06F2212/621 , G06F2212/622
摘要： A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions are applied to the vector that each produces a state signal including a different number of states based on the vector. A set status is determined that identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.

3. 发明授权

US09495300B2 Set selection of a set-associative storage container 有权
标题翻译：设置集合关联存储容器的选择
公开(公告)号：US09495300B2
公开(公告)日：2016-11-15
申请号：US15067305
申请日：2016-03-11
申请人： International Business Machines Corporation
发明人： Steven R. Carlough , Adam B. Collura
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F12/0822 , G06F12/121 , G06F12/122 , G06F12/128 , G06F2212/1044 , G06F2212/601 , G06F2212/6032 , G06F2212/621 , G06F2212/622
摘要： A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
摘要翻译：计算机实现的方法包括生成作为随机数的向量。将两个或更多个残差函数应用于向量以产生包括不同数量状态的状态信号。确定计算机系统中的集合关联存储容器的设置状态。设置状态标识是否启用或禁用了组关联存储容器的每一组。选择状态信号中的一个具有与启用的集合的数量相同数量的状态。所选择的状态信号被映射到能够将所选状态信号的每个状态分配给被启用的集合中的相应一个的集合。基于映射输出集合关联存储容器的集合选择，以随机选择从集合关联存储容器启用的集合之一。

4. 发明申请

US20160239301A1 SPECULATIVE BRANCH HANDLING FOR TRANSACTION ABORT 有权
公开(公告)号：US20160239301A1
公开(公告)日：2016-08-18
申请号：US14621513
申请日：2015-02-13
申请人： International Business Machines Corporation
发明人： Michael Billeci , James J. Bonanno , Adam B. Collura , Christian Jacobi , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/46 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F9/466 , G06F9/467
摘要： Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.

5. 发明申请

US20160092225A1 CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR 有权
标题翻译：同时进行多种处理器的检查
公开(公告)号：US20160092225A1
公开(公告)日：2016-03-31
申请号：US14830804
申请日：2015-08-20
申请人： International Business Machines Corporation
发明人： Adam B. Collura , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： According to an aspect, a method of checkpoint acceleration in a simultaneous multithreading (SMT) processor includes executing one or more threads in a processing pipeline of a processor core of the SMT processor, where the processing pipeline includes a completion stage followed by a checkpoint stage. A list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle is stored in a backlog queue. One or more of the next-to-complete groups of instructions are driven from the backlog queue to the checkpoint stage based on one or more completion indicators identifying which of the next-to-complete groups of instructions actually completed.
摘要翻译：根据一方面，同时多线程（SMT）处理器中的检查点加速的方法包括在SMT处理器的处理器核心的处理流水线中执行一个或多个线程，其中处理流水线包括完成阶段，后跟检查点阶段。待预定在即将到来的周期中完成的一个或多个线程的下一组完整指令组的列表存储在积压队列中。基于一个或多个完成指示符，一个或多个下一个完成的指令组从积压队列驱动到检查点阶段，该完成指示符标识下一个到完成的指令组中的哪一个实际完成。

6. 发明申请

US20160092224A1 CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR 有权
标题翻译：同时进行多种处理器的检查
公开(公告)号：US20160092224A1
公开(公告)日：2016-03-31
申请号：US14502229
申请日：2014-09-30
申请人： International Business Machines Corporation
发明人： Adam B. Collura , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： According to an aspect, a system for checkpoint acceleration in a simultaneous multithreading (SMT) processor includes circuitry of a processor core of the SMT processor to execute one or more threads in a processing pipeline. The processing pipeline includes a completion stage followed by a checkpoint stage. The system also includes a checkpoint accelerator disposed between the completion stage and the checkpoint stage. The checkpoint accelerator includes a backlog queue that stores a list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle. The checkpoint accelerator also includes a selection control that drives one or more of the next-to-complete groups of instructions from the backlog queue to the checkpoint stage based on one or more completion indicators that identify which of the next-to-complete groups of instructions actually completed.
摘要翻译：根据一个方面，用于同时多线程（SMT）处理器中的检查点加速的系统包括SMT处理器的处理器核心的电路，以在处理流水线中执行一个或多个线程。处理流水线包括完成阶段，随后是检查点阶段。该系统还包括设在完成阶段和检查点阶段之间的检查点加速器。检查点加速器包括积压队列，其存储来自预期在即将到来的周期中完成的一个或多个线程的下一组完成指令组的列表。检查点加速器还包括选择控制，该选择控制基于一个或多个完成指示符将一个或多个下一个到完成的指令组从积压队列驱动到检查点阶段，所述一个或多个完成指示符识别下一个到完成组中的哪一个说明实际完成。

7. 发明授权

US10437597B2 Silent mode and resource reassignment in branch prediction logic 有权
公开(公告)号：US10437597B2
公开(公告)日：2019-10-08
申请号：US14848498
申请日：2015-09-09
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Adam B. Collura , Daniel Lipetz , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38 , G06F9/30
摘要： A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.

8. 发明申请

US20180173429A1 PREDICTIVE SCHEDULER FOR MEMORY RANK SWITCHING 审中-公开
公开(公告)号：US20180173429A1
公开(公告)日：2018-06-21
申请号：US15659863
申请日：2017-07-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： James J. Bonanno , Michael J. Cadigan, JR. , Adam B. Collura , Daniel Lipetz , Patrick J. Meaney , Craig R. Walters
IPC分类号： G06F3/06 , G11C11/4091 , G11C11/406
CPC分类号： G06F3/0611 , G06F3/0632 , G06F3/0659 , G06F3/0673 , G06F13/16 , G11C5/04 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

9. 发明授权

US09720694B2 Silent mode and resource reassignment in branch prediction logic for branch instructions within a millicode routine 有权
公开(公告)号：US09720694B2
公开(公告)日：2017-08-01
申请号：US15254040
申请日：2016-09-01
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Adam B. Collura , Daniel Lipetz , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/30185 , G06F9/30189 , G06F9/3806 , G06F9/3842 , G06F9/3844 , G06F9/3851
摘要： A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.

10. 发明授权

US09606805B1 Accuracy of operand store compare prediction using confidence counter 有权
公开(公告)号：US09606805B1
公开(公告)日：2017-03-28
申请号：US14886465
申请日：2015-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Khary J. Alexander , Jane H. Bartik , Jatin Bhartia , James J. Bonanno , Adam B. Collura , Jang-Soo Lee , James R. Mitchell , Anthony Saporito
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30021 , G06F9/30043 , G06F9/30058 , G06F9/30145 , G06F9/3834 , G06F9/3838 , G06F9/3844 , G06F9/3855 , G06F9/3861
摘要： Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.

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