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1. 发明授权

US10534611B2 Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV) 有权
公开(公告)号：US10534611B2
公开(公告)日：2020-01-14
申请号：US14448030
申请日：2014-07-31
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Matthias D. Heizmann , Daniel Lipetz , Brian R. Prasky
IPC分类号： G06F9/38
摘要： Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

2. 发明申请

US20180165094A1 BRANCH PREDICTOR SEARCH QUALIFICATION USING STREAM LENGTH PREDICTION 审中-公开
公开(公告)号：US20180165094A1
公开(公告)日：2018-06-14
申请号：US15376847
申请日：2016-12-13
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Michael J. Cadigan, Jr. , Adam B. Collura , Daniel Lipetz
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3848
摘要： A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.

3. 发明授权

US09898299B2 Dynamic thread sharing in branch prediction structures 有权
公开(公告)号：US09898299B2
公开(公告)日：2018-02-20
申请号：US14820090
申请日：2015-08-06
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Daniel Lipetz , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38 , G06F9/40 , G06F9/44 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30058 , G06F9/3806 , G06F9/3844 , G06F9/3851 , G06F9/4806
摘要： Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

4. 发明授权

US09690587B2 Variable updates of branch prediction states 有权
公开(公告)号：US09690587B2
公开(公告)日：2017-06-27
申请号：US14247813
申请日：2014-04-08
申请人： International Business Machines Corporation
发明人： Narasimha R. Adiga , James J. Bonanno , Ashutosh Misra , Anthony Saporito
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/30061 , G06F9/30145 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.

5. 发明申请

US20160239309A1 BRANCH TARGET BUFFER COLUMN PREDICTOR 审中-公开
标题翻译：分支目标缓冲区预测器
公开(公告)号：US20160239309A1
公开(公告)日：2016-08-18
申请号：US14620960
申请日：2015-02-12
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Brian W. Curran , Daniel B. Lipetz , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3848
摘要： A processor receives a first instruction with a first instruction address within a first instruction stream. The processor selects a row of a branch target buffer and a row of a one-dimensional array based on the first instruction address. The processor reads information in the current row of the one-dimensional array, where the current row of one-dimensional array includes a first target address and a column of the row of the branch target buffer expected to contain a second target address. The processor receives a second instruction within a second instruction stream, which includes a second instruction address equal to the first target address. The processor reads information included in the row of the branch target buffer, where the information included the row of the branch target buffer includes the second target address. The processor encounters a branch including a third target address within the first instruction stream.
摘要翻译：处理器在第一指令流内接收具有第一指令地址的第一指令。处理器基于第一指令地址选择分支目标缓冲器的行和一维阵列的行。处理器读取一维阵列的当前行中的信息，其中一维阵列的当前行包括预期包含第二目标地址的第一目标地址和分支目标缓冲器的行的列。处理器在第二指令流内接收第二指令，该指令包括等于第一目标地址的第二指令地址。处理器读取包括在分支目标缓冲器的行中的信息，其中包括分支目标缓冲器的行的信息包括第二目标地址。处理器遇到包括第一指令流内的第三目标地址的分支。

6. 发明申请

US20160239301A1 SPECULATIVE BRANCH HANDLING FOR TRANSACTION ABORT 有权
公开(公告)号：US20160239301A1
公开(公告)日：2016-08-18
申请号：US14621513
申请日：2015-02-13
申请人： International Business Machines Corporation
发明人： Michael Billeci , James J. Bonanno , Adam B. Collura , Christian Jacobi , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/46 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F9/466 , G06F9/467
摘要： Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.

7. 发明授权

US09250909B2 Fast index tree for accelerated branch prediction 有权
标题翻译：用于加速分支预测的快速索引树
公开(公告)号：US09250909B2
公开(公告)日：2016-02-02
申请号：US13784880
申请日：2013-03-05
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/38 , G06F9/3806 , G06F9/3844
摘要： Embodiments relate to using a fast index tree for accelerated branch prediction. A computer-implemented method includes determining, by a computer, that searching of a branch target buffer is to be performed under FIT control. A current search address is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from a FIT structure. The searching is re-indexed based on the FIT next-search address. Based on locating the branch prediction, the searching is continued under FIT control with the current search address set based on the FIT next-search address. Based on failing to locate the branch prediction, the searching is re-indexed with the saved current search address, and the searching is performed without FIT control.
摘要翻译：实施例涉及使用用于加速分支预测的快速索引树。计算机实现的方法包括由计算机确定在FIT控制下执行对分支目标缓冲器的搜索。当前的搜索地址被保存。在保存的当前搜索地址搜索分支目标缓冲区以进行分支预测。基于从FIT结构中读取预测分支的下一个搜索水平的读取分支和分支未采用的路径来确定FIT下一个搜索地址。基于FIT下一个搜索地址重新索引搜索。基于定位分支预测，基于FIT下一搜索地址设置的当前搜索地址，在FIT控制下继续搜索。基于未能定位分支预测，用保存的当前搜索地址重新索引搜索，并且在不进行FIT控制的情况下执行搜索。

8. 发明申请

US20150019849A1 SEMI-EXCLUSIVE SECOND-LEVEL BRANCH TARGET BUFFER 有权
标题翻译： SEMI独家二级分支目标缓冲区
公开(公告)号：US20150019849A1
公开(公告)日：2015-01-15
申请号：US14501093
申请日：2014-09-30
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30145 , G06F9/3808
摘要： Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB2 having a memory region corresponding to a search request. Based on locating the entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to a BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to a BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2.
摘要翻译：实施例涉及半独有的第二级分支目标缓冲器。一个方面包括用于半独占二级分支目标缓冲器的计算机实现的方法。该方法包括执行搜索以定位具有对应于搜索请求的存储区域的BTB2中的条目。基于在BTB2中定位条目，从BTB2到BTBP执行定位条目的批量传输。更新与定位条目关联的状态，以鼓励BTB1和BTB2之间的排他性。基于将BTBP条目从BTBP转移到BTB1，BTB1条目从BTB1被移出。驱逐的BTB1条目从BTB1转移到BTB2。

9. 发明授权

US08914593B2 Counter-based entry invalidation for metadata previous write queue 有权
公开(公告)号：US08914593B2
公开(公告)日：2014-12-16
申请号：US14101437
申请日：2013-12-10
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Brian R. Prasky
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12 , G06F11/07
CPC分类号： G06F12/0891 , G06F11/076 , G06F12/00 , G06F12/0802 , G06F12/12 , G06F13/385
摘要： Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.

10. 发明授权

US08898427B2 Target buffer address region tracking 有权
标题翻译：目标缓冲区地址区域跟踪
公开(公告)号：US08898427B2
公开(公告)日：2014-11-25
申请号：US14088555
申请日：2013-11-25
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Brian R. Prasky , Aaron Tsai
IPC分类号： G06F12/02 , G06F9/38
CPC分类号： G06F12/02 , G06F9/3806 , G11C29/76
摘要： Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as a same range and a different range to form a predicted target address range defining an address region associated with an entry in the target buffer. Based on determining that the restart address matches the first stored address, the first stored address is identified as the same range and the second stored address is identified as the different range. Based on determining that the restart address matches the second stored address, the first stored address is identified as the different range and the second stored address is identified as the same range.
摘要翻译：实施例涉及目标缓冲器地址区域跟踪。一个方面包括接收重启地址，并且由处理电路将重启地址与第一存储地址和第二存储地址进行比较。处理电路确定将第一和第二存储的地址中的哪一个识别为相同的范围和不同的范围，以形成定义与目标缓冲器中的条目相关联的地址区域的预测目标地址范围。基于确定重启地址与第一存储地址匹配，第一存储地址被标识为相同的范围，并且将第二存储地址识别为不同的范围。基于确定重新启动地址与第二存储地址匹配，将第一存储地址识别为不同的范围，并将第二存储地址识别为相同的范围。

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