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1. 发明申请

WO2021236143A1 RADAR APPARATUS, SYSTEM, AND METHOD 审中-公开
公开(公告)号：WO2021236143A1
公开(公告)日：2021-11-25
申请号：PCT/US2020/052423
申请日：2020-09-24
申请人： INTEL CORPORATION
发明人： SHIN, Woorim , PELLERANO, Stefano , LEVINGER, Run , LANDSBERG, Naftali , GORDON, Meir , WEISMAN, Nir , SHUMAKER, Evgeny , RAHMAN, Mustafijur , OHEV ZION, Dan , NAHMANNY, Danniel , HOROVITZ, Gil , BERSHANSKY, Sergey , ASAF, Omer
IPC分类号： G01S7/03 , G01S13/931 , G01S7/40
摘要： Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) chains to transmit radar Tx signals, and a plurality of Receive (Rx) chains to process radar Rx signals. For example, the radar Rx signals may be based on the radar Tx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.

2. 发明申请

WO2019004993A1 FREQUENCY ESTIMATION 审中-公开
公开(公告)号：WO2019004993A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/039197
申请日：2017-06-26
申请人： INTEL CORPORATION
发明人： ZUR, Sarit , KUSHNIR, Igal , HOROVITZ, Gil , BANIN, Rotem , BERSHANSKY, Sergey
IPC分类号： G01R23/02 , G01R23/10 , G01R23/14 , H03L7/06
摘要： A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

3. 发明公开

EP4154030A1 RADAR APPARATUS, SYSTEM, AND METHOD 审中-实审
公开(公告)号：EP4154030A1
公开(公告)日：2023-03-29
申请号：EP20936538.6
申请日：2020-09-24
申请人： INTEL Corporation
发明人： SHIN, Woorim , PELLERANO, Stefano , LEVINGER, Run , LANDSBERG, Naftali , GORDON, Meir , WEISMAN, Nir , SHUMAKER, Evgeny , RAHMAN, Mustafijur , OHEV ZION, Dan , NAHMANNY, Danniel , HOROVITZ, Gil , BERSHANSKY, Sergey , ASAF, Omer
IPC分类号： G01S7/03 , G01S13/931 , G01S7/40

4. 发明申请

WO2020131218A1 ADAPTIVE TIME-TO-DIGITAL CONVERTER AND METHOD 审中-公开
公开(公告)号：WO2020131218A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/058278
申请日：2019-10-28
申请人： INTEL CORPORATION
发明人： HOROVITZ, Gil , FARBER, Aryeh , MACHLUF, Nisim , SHUMAKER, Evgeny , KUSHNIR, Igal
IPC分类号： H03L7/085 , G04F10/00
摘要： Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.

5. 发明申请

WO2020112277A1 SYSTEMS AND METHODS FOR MITIGATION OF NONLINEARITY RELATED PHASE NOISE DEGRADATIONS 审中-公开
公开(公告)号：WO2020112277A1
公开(公告)日：2020-06-04
申请号：PCT/US2019/057566
申请日：2019-10-23
申请人： INTEL CORPORATION
发明人： SHUMAKER, Evgeny , HOROVITZ, Gil
IPC分类号： H03L7/08 , H04B1/40
摘要： A PLL system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the TDC is disclosed. The system includes a phase modulation circuit configured to generate phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

6. 发明申请

WO2018057153A1 LOCAL OSCILLATOR SIGNAL GENERATION USING OPPORTUNISTIC SYNTHESIZER TO CLOCK DIGITAL SYNTHESIS 审中-公开
标题翻译：用机械合成器实现数字综合的局部振荡信号发生
公开(公告)号：WO2018057153A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/047100
申请日：2017-08-16
申请人： INTEL CORPORATION
发明人： KUSHNIR, Igal , HOROVITZ, Gil , ZUR, Sarit
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H04B1/38 , H03B21/00 , H03B21/01 , H03L7/08 , H03L7/099 , H03L2207/06 , H04B17/11 , H04L27/205
摘要： Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.
摘要翻译：提供用于产生本地振荡器（LO）信号的控制电路。合成器控制电路被配置为控制合成器电路以产生具有第一频率的模拟振荡器信号，在该第一频率处相位噪声被最小化。 DS控制电路被配置为当DS电路由具有第一频率的振荡器信号计时时，生成控制字或消息以使DS电路生成具有期望频率的数字DS信号。所需频率与LO信号频率成正比。由DS电路生成的数字DS信号用于生成LO信号。因此，选择用于DS电路时钟的第一个频率来优化振荡器，而不是与LO频率有某种关系。另外，可以使用单个合成器来同时产生许多LO信号。

7. 发明公开

EP3975431A1 APPARATUS, SYSTEM AND METHOD FOR GENERATING AN OUTPUT OSCILLATOR SIGNAL, TRANSCEIVER, MOBILE DEVICE AND BASE STATION 审中-公开
公开(公告)号：EP3975431A1
公开(公告)日：2022-03-30
申请号：EP21192791.8
申请日：2021-08-24
申请人： INTEL Corporation
发明人： DEGANI, Ofir , HOROVITZ, Gil , SHUMAKER, Evgeny , BERSHANSKY, Sergey , FARBER, Aryeh , GERTMAN, Igor , LEVINGER, Run
IPC分类号： H03L7/22 , H03L7/16 , H03L7/087 , H03L7/099
摘要： An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.

8. 发明公开

EP3646041A1 FREQUENCY ESTIMATION 审中-公开
公开(公告)号：EP3646041A1
公开(公告)日：2020-05-06
申请号：EP17916383.7
申请日：2017-06-26
申请人： INTEL Corporation
发明人： ZUR, Sarit , KUSHNIR, Igal , HOROVITZ, Gil , BANIN, Rotem , BERSHANSKY, Sergey
IPC分类号： G01R23/02 , G01R23/10 , G01R23/14 , H03L7/06

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