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1. 发明申请

WO2018057153A1 LOCAL OSCILLATOR SIGNAL GENERATION USING OPPORTUNISTIC SYNTHESIZER TO CLOCK DIGITAL SYNTHESIS 审中-公开
标题翻译：用机械合成器实现数字综合的局部振荡信号发生
公开(公告)号：WO2018057153A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/047100
申请日：2017-08-16
申请人： INTEL CORPORATION
发明人： KUSHNIR, Igal , HOROVITZ, Gil , ZUR, Sarit
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H04B1/38 , H03B21/00 , H03B21/01 , H03L7/08 , H03L7/099 , H03L2207/06 , H04B17/11 , H04L27/205
摘要： Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.
摘要翻译：提供用于产生本地振荡器（LO）信号的控制电路。合成器控制电路被配置为控制合成器电路以产生具有第一频率的模拟振荡器信号，在该第一频率处相位噪声被最小化。 DS控制电路被配置为当DS电路由具有第一频率的振荡器信号计时时，生成控制字或消息以使DS电路生成具有期望频率的数字DS信号。所需频率与LO信号频率成正比。由DS电路生成的数字DS信号用于生成LO信号。因此，选择用于DS电路时钟的第一个频率来优化振荡器，而不是与LO频率有某种关系。另外，可以使用单个合成器来同时产生许多LO信号。

2. 发明申请

WO2022066255A1 SELF-INTERFERENCE CANCELLER 审中-公开
公开(公告)号：WO2022066255A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/039169
申请日：2021-06-25
申请人： INTEL CORPORATION
发明人： BENJAMIN, Ofer , BOROKHOVICH, Eli , CARLTON, Brent , DEGANI, Ofir , KRONFELD, Ronen , PELLERANO, Stefano , RAHMAN, Mustafijur , RESHEF, Ehud , ZUR, Sarit
IPC分类号： H04B1/10 , H04B1/06 , G06F7/00 , H04B1/12 , H04B1/02
摘要： A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.

3. 发明申请

WO2019004993A1 FREQUENCY ESTIMATION 审中-公开
公开(公告)号：WO2019004993A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/039197
申请日：2017-06-26
申请人： INTEL CORPORATION
发明人： ZUR, Sarit , KUSHNIR, Igal , HOROVITZ, Gil , BANIN, Rotem , BERSHANSKY, Sergey
IPC分类号： G01R23/02 , G01R23/10 , G01R23/14 , H03L7/06
摘要： A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

4. 发明公开

EP3646041A1 FREQUENCY ESTIMATION 审中-公开
公开(公告)号：EP3646041A1
公开(公告)日：2020-05-06
申请号：EP17916383.7
申请日：2017-06-26
申请人： INTEL Corporation
发明人： ZUR, Sarit , KUSHNIR, Igal , HOROVITZ, Gil , BANIN, Rotem , BERSHANSKY, Sergey
IPC分类号： G01R23/02 , G01R23/10 , G01R23/14 , H03L7/06

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