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1. 发明申请

WO2013095521A1 INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM 审中-公开
标题翻译：指令处理程序，方法和系统处理BLAKE安全冲洗算法
公开(公告)号：WO2013095521A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066898
申请日：2011-12-22
申请人： INTEL CORPORATION , WOLRICH, Gilbert, M. , YAP, Kirk, S. , GUILFORD, James, D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
发明人： WOLRICH, Gilbert, M. , YAP, Kirk, S. , GUILFORD, James, D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
IPC分类号： H04L9/28 , H04L9/12
CPC分类号： H04L9/28 , G06F9/30007 , G06F9/30036 , G06F21/72 , H04L9/0643 , H04L2209/122
摘要： A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.
摘要翻译：一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。该指令还指示具有表示消息和常数数据的数据元素的第二源。响应该指令，结果存储在指令指示的目的地中。结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

2. 发明申请

WO2013112118A2 INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING IN A 256 BIT DATA PATH 审中-公开
标题翻译：在256位数据路径中执行JH密码碎化的指令
公开(公告)号：WO2013112118A2
公开(公告)日：2013-08-01
申请号：PCT/US2011/066719
申请日：2011-12-22
申请人： INTEL CORPORATION , WOLRICH, Gilbert, M. , YAP, Kirk, S. , GOPAL, Vinodh , GUILFORD, James, D. , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
发明人： WOLRICH, Gilbert, M. , YAP, Kirk, S. , GOPAL, Vinodh , GUILFORD, James, D. , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
IPC分类号： G06F17/10 , G06F9/06 , G06F13/14
CPC分类号： H04L9/14 , G06F9/30007 , G06F9/30032 , G06F9/30036 , G06F9/3893 , G06F21/602 , H04L9/3239
摘要： A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
摘要翻译：描述了一种方法。该方法包括执行一个或多个JH_SBOX_L指令以对JH状态执行S-Box映射和线性（L）变换，并且一旦执行了一个或多个JH_P指令就对JH状态执行置换功能，一旦S盒映射和 L转换已经完成。

3. 发明申请

WO2012078378A2 ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS 审中-公开
标题翻译：通过指令交互和/或多个缓冲区的并发处理来提高性能
公开(公告)号：WO2012078378A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/062127
申请日：2011-11-23
申请人： INTEL CORPORATION , GUILFORD, James, D. , FEGHALI, Wajdi, K. , GOPAL, Vinodh , WOLRICH, Gilbert, M. , OZTURK, Erdinc , DIXON, Martin, G. , KARAKOYUNLU, Deniz , AKDEMIR, Kahraman, D.
发明人： GUILFORD, James, D. , FEGHALI, Wajdi, K. , GOPAL, Vinodh , WOLRICH, Gilbert, M. , OZTURK, Erdinc , DIXON, Martin, G. , KARAKOYUNLU, Deniz , AKDEMIR, Kahraman, D.
IPC分类号： G06F9/44 , G06F9/46 , G06F9/06
CPC分类号： G06F9/3851 , G06F9/30109 , G06F9/4843
摘要： An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.
摘要翻译：实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。第一指令列表的执行可以至少部分地由第一函数调用的调用产生。第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。这些部分可以至少部分地由电路的一个或多个执行单元同时执行。第二和第三指令列表可以至少部分地实现适合于通过单独的相应功能调用来调用的相应算法。并行处理可以至少部分地涉及互补算法。

4. 发明申请

WO2007078923A2 CRYPTOGRAPHY PROCESSING UNITS AND MULTIPLIER 审中-公开
标题翻译：图像处理单元和多路复用器
公开(公告)号：WO2007078923A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048293
申请日：2006-12-18
申请人： INTEL CORPORATION , HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
发明人： HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
IPC分类号： G06F9/38
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

5. 发明申请

WO2013095615A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 审中-公开
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：WO2013095615A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067092
申请日：2011-12-23
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
发明人： GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
IPC分类号： H03M7/30
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

6. 发明申请

WO2007078939A2 MULTIPLIER 审中-公开
标题翻译：乘数
公开(公告)号：WO2007078939A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048417
申请日：2006-12-18
申请人： INTEL CORPORATION , FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
发明人： FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
IPC分类号： G06F7/525
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：一般来说，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的集合具有对第一操作数的访问和第二操作数的乘法，第一操作数具有多个段，第二操作数具有多个段具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的各个乘法器，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器组中不同的乘法器的输出。乘法器还包括耦合到逻辑的累加器。

7. 发明申请

WO2008027735A1 SYSTEM AND METHOD FOR MULTI-PRECISION DIVISION 审中-公开
标题翻译：多精度部分的系统和方法
公开(公告)号：WO2008027735A1
公开(公告)日：2008-03-06
申请号：PCT/US2007/076149
申请日：2007-08-16
申请人： INTEL CORPORATION , GOPAL, Vinodh , BACE, Matt , GAUBATZ, Gunnar , WOLRICH, Gilbert, M.
发明人： GOPAL, Vinodh , BACE, Matt , GAUBATZ, Gunnar , WOLRICH, Gilbert, M.
IPC分类号： H04L9/18
CPC分类号： G06F7/535 , G06F2207/3896
摘要： The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行多精度分割的系统和方法。根据一个实施例的方法可以包括通过将具有最高有效位和/或最低有效位的模数乘以等于1的模数和模数的商近似来生成第一乘积。该方法还可以包括生成第一产品的1的补码，通过乘以1的补码和商近似来生成第二乘积，归一化和截断第二乘积以获得商，并将商存储在存储器中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

8. 发明申请

WO2014051747A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 审中-公开
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：WO2014051747A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/045794
申请日：2013-06-14
申请人： INTEL CORPORATION
发明人： WOLRICH, Gilbert, M. , YAP, Kirk, S. , GOPAL, Vinodh
IPC分类号： G06F9/30
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the fist instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。所述处理器还包括第一执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用从第三指令获得的第一旋转值基于所述奇数字和偶数字执行所述第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

9. 发明公开

EP1966680A2 MULTIPLIER 有权
标题翻译：乘数
公开(公告)号：EP1966680A2
公开(公告)日：2008-09-10
申请号：EP06845803.3
申请日：2006-12-18
申请人： Intel Corporation
发明人： FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
IPC分类号： G06F7/525
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：通常，在一个方面，本公开描述了一种乘法器，该乘法器包括并行配置的一组多个乘法器，其中多个乘法器的集合可以访问第一操作数和第二操作数以便相乘，第一操作数具有多个段并且第二操作数操作数有多个段。乘法器还包括逻辑，用于重复提供第二操作数的单个段到该组多个乘法器中的每个乘法器，并且将第一操作数的多个相应段提供给该多个乘法器集中的相应乘法直到第二个操作数已经与第一个操作数的每个段一起提供。该逻辑至少部分地基于第一操作数内的各个段的位置来移位该多个乘法器组中的不同者的输出。乘法器还包括一个连接到逻辑的累加器。

10. 发明授权

EP1966680B1 MULTIPLIER 有权
标题翻译：乘数
公开(公告)号：EP1966680B1
公开(公告)日：2010-10-13
申请号：EP06845803.3
申请日：2006-12-18
申请人： Intel Corporation
发明人： FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
IPC分类号： G06F7/525
CPC分类号： G06F7/5275

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