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1. 发明申请

WO2013095521A1 INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM 审中-公开
标题翻译：指令处理程序，方法和系统处理BLAKE安全冲洗算法
公开(公告)号：WO2013095521A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066898
申请日：2011-12-22
申请人： INTEL CORPORATION , WOLRICH, Gilbert, M. , YAP, Kirk, S. , GUILFORD, James, D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
发明人： WOLRICH, Gilbert, M. , YAP, Kirk, S. , GUILFORD, James, D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
IPC分类号： H04L9/28 , H04L9/12
CPC分类号： H04L9/28 , G06F9/30007 , G06F9/30036 , G06F21/72 , H04L9/0643 , H04L2209/122
摘要： A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.
摘要翻译：一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。该指令还指示具有表示消息和常数数据的数据元素的第二源。响应该指令，结果存储在指令指示的目的地中。结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

2. 发明申请

WO2013112118A2 INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING IN A 256 BIT DATA PATH 审中-公开
标题翻译：在256位数据路径中执行JH密码碎化的指令
公开(公告)号：WO2013112118A2
公开(公告)日：2013-08-01
申请号：PCT/US2011/066719
申请日：2011-12-22
申请人： INTEL CORPORATION , WOLRICH, Gilbert, M. , YAP, Kirk, S. , GOPAL, Vinodh , GUILFORD, James, D. , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
发明人： WOLRICH, Gilbert, M. , YAP, Kirk, S. , GOPAL, Vinodh , GUILFORD, James, D. , OZTURK, Erdinc , GULLEY, Sean, M. , FEGHALI, Wajdi, K. , DIXON, Martin, G.
IPC分类号： G06F17/10 , G06F9/06 , G06F13/14
CPC分类号： H04L9/14 , G06F9/30007 , G06F9/30032 , G06F9/30036 , G06F9/3893 , G06F21/602 , H04L9/3239
摘要： A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
摘要翻译：描述了一种方法。该方法包括执行一个或多个JH_SBOX_L指令以对JH状态执行S-Box映射和线性（L）变换，并且一旦执行了一个或多个JH_P指令就对JH状态执行置换功能，一旦S盒映射和 L转换已经完成。

3. 发明申请

WO2012078378A2 ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS 审中-公开
标题翻译：通过指令交互和/或多个缓冲区的并发处理来提高性能
公开(公告)号：WO2012078378A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/062127
申请日：2011-11-23
申请人： INTEL CORPORATION , GUILFORD, James, D. , FEGHALI, Wajdi, K. , GOPAL, Vinodh , WOLRICH, Gilbert, M. , OZTURK, Erdinc , DIXON, Martin, G. , KARAKOYUNLU, Deniz , AKDEMIR, Kahraman, D.
发明人： GUILFORD, James, D. , FEGHALI, Wajdi, K. , GOPAL, Vinodh , WOLRICH, Gilbert, M. , OZTURK, Erdinc , DIXON, Martin, G. , KARAKOYUNLU, Deniz , AKDEMIR, Kahraman, D.
IPC分类号： G06F9/44 , G06F9/46 , G06F9/06
CPC分类号： G06F9/3851 , G06F9/30109 , G06F9/4843
摘要： An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.
摘要翻译：实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。第一指令列表的执行可以至少部分地由第一函数调用的调用产生。第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。这些部分可以至少部分地由电路的一个或多个执行单元同时执行。第二和第三指令列表可以至少部分地实现适合于通过单独的相应功能调用来调用的相应算法。并行处理可以至少部分地涉及互补算法。

4. 发明申请

WO2018063717A1 HARDWARE ACCELERATORS AND METHODS FOR OFFLOAD OPERATIONS 审中-公开
标题翻译：硬件加速器和卸载操作方法
公开(公告)号：WO2018063717A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049407
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： DRYSDALE, Tracy, Garrett , GOPAL, Vinodh , GUILFORD, James, D.
IPC分类号： G06F9/30 , G06F12/084
摘要： Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.
摘要翻译：描述与卸载操作有关的方法和装置。在一个实施例中，硬件处理器包括执行线程和卸载操作的核心; 以及执行操作的第一和第二硬件加速器，其中第一和第二硬件加速器耦合到共享缓冲器以存储来自第一硬件加速器的输出数据并将输出数据作为输入数据提供给第二硬件加速器，输入缓冲器所述第二硬件加速器的输出缓冲器描述符阵列具有用于每个相应的共享缓冲器的条目，所述第二硬件加速器的输入缓冲器响应描述符阵列具有用于每个相应共享缓冲器的对应响应条目，每个相应共享缓冲器的入口，以及第一硬件加速器的输出缓冲器响应描述符阵列以及每个相应共享缓冲器的对应响应入口。

5. 发明公开

EP3519946A1 HARDWARE ACCELERATORS AND METHODS FOR OFFLOAD OPERATIONS 有权
公开(公告)号：EP3519946A1
公开(公告)日：2019-08-07
申请号：EP17857143.6
申请日：2017-08-30
申请人： Intel Corporation
发明人： DRYSDALE, Tracy, Garrett , GOPAL, Vinodh , GUILFORD, James, D.
IPC分类号： G06F9/30 , G06F12/084

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