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1. 发明申请

WO2013095657A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR BLEND AND PERMUTE FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供向量混合和绝对功能
公开(公告)号：WO2013095657A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067245
申请日：2011-12-23
申请人： INTEL CORPORATION , VALENTINE, Robert , TOLL, Bret L. , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar J. , CORBAL, Jesus
发明人： VALENTINE, Robert , TOLL, Bret L. , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar J. , CORBAL, Jesus
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/3887
摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
摘要翻译：提供向量混合和置换功能，响应于指令：包括存储向量元素的字段的目的地向量寄存器，第一向量寄存器，向量元素大小，第二向量寄存器和第三操作数。指数从第二个寄存器中的字段读取。每个索引具有第一选择器部分和第二选择器部分。对应的未屏蔽向量元素被存储到目的地寄存器的字段，其中响应于具有第一值的相应第一选择器部分的每个向量元素从第一寄存器的相应数据字段被复制到中间向量，并且响应于具有第二值的相应的第一选择器部分从第三操作数的相应数据字段复制到中间向量。然后，由对应的第二选择器部分索引的中间向量中的数据字段替换目的地的未屏蔽的数据字段。

2. 发明申请

WO2013101124A1 PACKED DATA OPERATION MASK COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：包装数据操作掩码比较处理器，方法，系统和指令
公开(公告)号：WO2013101124A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067972
申请日：2011-12-29
申请人： INTEL CORPORATION , TOLL, Bret L. , VALENTINE, Robert , CORBAL, Jesus , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
发明人： TOLL, Bret L. , VALENTINE, Robert , CORBAL, Jesus , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
IPC分类号： G06F9/06 , G06F9/30 , G06F13/14
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译：接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。否则将第一个标志修改为第二个值。如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。否则将第二个标志修改为第四个值。

3. 发明申请

WO2013095637A1 APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS 审中-公开
标题翻译：装置和方法的改进的准则说明
公开(公告)号：WO2013095637A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067210
申请日：2011-12-23
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J.
发明人： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J.
IPC分类号： G06F1/00 , G06F9/30 , G06F9/305
CPC分类号： G06F9/30029 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
摘要翻译：描述了具有指令执行逻辑电路的设备。指令执行逻辑电路具有输入向量元素路由电路，以针对三个不同指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素路由到输出向量元素位置，输入矢量元素位置，可用于输出矢量元素。输出矢量元素和每个输入矢量元素位置是三个不同指令的三个可用位宽中的一个。该装置还包括耦合到输入矢量元件路由电路的屏蔽层电路，以屏蔽由输入矢量路由元件电路创建的数据结构。屏蔽层电路被设计为以三个不同的粒度级进行掩模，这些粒度级对应于三个可用比特宽度。

4. 发明申请

WO2013095609A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER 审中-公开
标题翻译：用于将掩码寄存器转换为矢量寄存器的系统，设备和方法
公开(公告)号：WO2013095609A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067086
申请日：2011-12-23
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
发明人： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a vector register in response to a single vector packed convert a mask register to a vector register instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.
摘要翻译：用于在计算机处理器中执行的系统，装置和方法，用于响应于单向量压缩将掩码寄存器转换为向量寄存器，将掩码寄存器转换为向量寄存器指令，所述向量寄存器指令包括目的地向量寄存器操作数，源写入掩码寄存器操作数和操作码。

5. 发明申请

WO2013095610A1 APPARATUS AND METHOD FOR SHUFFLING FLOATING POINT OR INTEGER VALUES 审中-公开
标题翻译：浮动点或整数值的装置和方法
公开(公告)号：WO2013095610A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067087
申请日：2011-12-23
申请人： INTEL CORPORATION , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , ULIEL, Tal , TOLL, Bret L.
发明人： VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , ULIEL, Tal , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/38 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method are described for shuffling data elements from source registers to a destination register. For example, a method according to one embodiment includes the following operations: reading each mask bit stored in a mask data structure, the mask data structure containing mask bits associated with data elements of a destination register, the values usable for determining whether a masking operation or a shuffle operation should be performed on data elements stored within a first source register and a second source register; for each data element of the destination register, if a mask bit associated with the data element indicates that a shuffle operation should be performed, then shuffling data elements from the first source register and the second source register to the specified data element within the destination register; and if the mask bit indicates that a masking operation should be performed, then performing a specified masking operation with respect to the data element of the destination register.
摘要翻译：描述了将数据元素从源寄存器混合到目的地寄存器的装置和方法。例如，根据一个实施例的方法包括以下操作：读取存储在掩模数据结构中的每个掩码位，所述掩码数据结构包含与目的地寄存器的数据元素相关联的掩码位，可用于确定掩蔽操作或者应当对存储在第一源寄存器和第二源寄存器中的数据元素执行混洗操作; 对于目标寄存器的每个数据元素，如果与数据元素相关联的掩码位指示应当执行混洗操作，则将数据元素从第一源寄存器和第二源寄存器混洗到目标寄存器中的指定数据元素 ; 并且如果掩码位指示应当执行掩蔽操作，则对目的地寄存器的数据元素执行指定的掩蔽操作。

6. 发明申请

WO2014105214A1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY 审中-公开
标题翻译：方法，装置，说明和逻辑提供矢量地址冲突检测功能
公开(公告)号：WO2014105214A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048837
申请日：2013-06-30
申请人： INTEL CORPORATION , HUGHES, Christopher , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , GIRKAR, Milind B.
发明人： HUGHES, Christopher , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , GIRKAR, Milind B.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F9/30145 , G06F9/30185 , G06F9/3838 , G06F9/3887
摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突检测功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移量，并且在目标寄存器中的相应冲突掩码中，设置对应于少量数据的任何掩码位具有匹配偏移的重要数据字段。向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

7. 发明申请

WO2014051752A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONFLICT DETECTION AND BROADCASTING CONTENTS OF A REGISTER TO DATA ELEMENT POSITIONS OF ANOTHER REGISTER 审中-公开
标题翻译：用于执行冲突检测和广播内容的系统，设备和方法将其注册到其他注册机构的数据元素位置
公开(公告)号：WO2014051752A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/045996
申请日：2013-06-14
申请人： INTEL CORPORATION , HUGHES, Christopher J. , CHARNEY, Mark J. , CORBAL, Jesus , GIRKAR, Milind B. , OULD-AHMED-VALL, Elmoustapha , TOLL, Bret L. , VALENTINE, Robert
发明人： HUGHES, Christopher J. , CHARNEY, Mark J. , CORBAL, Jesus , GIRKAR, Milind B. , OULD-AHMED-VALL, Elmoustapha , TOLL, Bret L. , VALENTINE, Robert
IPC分类号： G06F12/02
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30043 , G06F9/30109
摘要： Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior to broadcasting.
摘要翻译：在计算机处理器中执行响应于包括源写入寄存器操作数，目的地向量寄存器操作数和操作码的单向量压缩广播指令进行广播数据的系统，装置和方法。在一些实施例中，源写入掩码寄存器的数据在广播之前是零扩展的。

8. 发明申请

WO2013095637A9 APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS 审中-公开
公开(公告)号：WO2013095637A9
公开(公告)日：2013-06-27
申请号：PCT/US2011/067210
申请日：2011-12-23
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
发明人： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F1/00 , G06F9/30 , G06F9/305
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

9. 发明申请

WO2013095630A1 APPARATUS AND METHOD OF IMPROVED EXTRACT INSTRUCTIONS BACKGROUND 审中-公开
标题翻译：改进的提取说明的装置和方法背景技术
公开(公告)号：WO2013095630A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067182
申请日：2011-12-23
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J.
发明人： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J.
IPC分类号： G06F9/30 , G06F9/305 , G06F1/00
CPC分类号： G06F9/30149 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30145
摘要： An apparatus is described that includes instruction execution logic circuitry to execute first, second, third and fourth instructions. Both the first instruction and the second instruction select a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups of the first and third instructions at a first granularity, where, respective resultants produced therewith are respective resultants of the first and third instructions. The masking circuitry is also to mask the first and second groups of the second and fourth instructions at a second granularity, where, respective resultants produced therewith are respective resultants of the second and fourth instructions.
摘要翻译：描述了包括执行第一，第二，第三和第四指令的指令执行逻辑电路的装置。第一指令和第二指令都从相应的第一和第二输入向量的多个第一非重叠部分之一中选择第一组输入向量元素。第一组具有第一位宽度。多个第一非重叠部分中的每一个具有与第一组相同的位宽度。第三指令和第四指令都从相应的第三和第四输入向量的多个第二非重叠部分之一中选择第二组输入向量元素。第二组具有比第一位宽大的第二位宽度。多个第二非重叠部分中的每一个具有与第二组相同的位宽度。该装置包括掩蔽层电路，以第一粒度掩蔽第一和第三指令的第一和第二组，其中由其产生的相应结果是第一和第三指令的相应结果。掩蔽电路还以第二粒度掩蔽第二和第四指令的第一和第二组，其中由其产生的相应结果是第二和第四指令的相应结果。

10. 发明申请

WO2013095612A1 APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER 审中-公开
标题翻译：从通用寄存器向矢量寄存器广播的装置和方法
公开(公告)号：WO2013095612A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067089
申请日：2011-12-23
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha. , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
发明人： OULD-AHMED-VALL, Elmoustapha. , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication.
摘要翻译：描述了用于从通用源寄存器到目的地向量寄存器的广播的装置和方法。例如，根据一个实施例的方法包括以下操作：选择要更新的目的地向量寄存器内的数据元素位置N; 如果将掩码指示符设置为第一指示，则将一组数据从通用源寄存器传送到目的地向量寄存器内的数据元素位置N; 并且如果掩模指示符被设置为第二指示，则将零值复制到目的地向量寄存器内的数据元素位置N，或者保持存储在目的地向量寄存器内的数据元素位置N内的现有值。

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