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1. 发明申请

WO2012040545A9 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
公开(公告)号：WO2012040545A9
公开(公告)日：2012-10-04
申请号：PCT/US2011052899
申请日：2011-09-23
申请人： INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
发明人： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30036
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

2. 发明申请

WO2012040665A2 VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP 审中-公开
标题翻译：在半导体芯片上实现的矢量逻辑减少操作
公开(公告)号：WO2012040665A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053153
申请日：2011-09-24
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
IPC分类号： G06F9/305 , G06F9/30 , G06F9/44 , G06F1/00
CPC分类号： G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
摘要翻译：描述半导体处理器。该半导体处理器包括执行逻辑缩减指令的逻辑电路。逻辑电路具有混合电路以搅拌矢量的元素以形成混合矢量。逻辑电路还具有矢量逻辑电路，以对所述矢量和所述调配矢量执行矢量逻辑运算。

3. 发明申请

WO2013095657A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR BLEND AND PERMUTE FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供向量混合和绝对功能
公开(公告)号：WO2013095657A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067245
申请日：2011-12-23
申请人： INTEL CORPORATION , VALENTINE, Robert , TOLL, Bret L. , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar J. , CORBAL, Jesus
发明人： VALENTINE, Robert , TOLL, Bret L. , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar J. , CORBAL, Jesus
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/3887
摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
摘要翻译：提供向量混合和置换功能，响应于指令：包括存储向量元素的字段的目的地向量寄存器，第一向量寄存器，向量元素大小，第二向量寄存器和第三操作数。指数从第二个寄存器中的字段读取。每个索引具有第一选择器部分和第二选择器部分。对应的未屏蔽向量元素被存储到目的地寄存器的字段，其中响应于具有第一值的相应第一选择器部分的每个向量元素从第一寄存器的相应数据字段被复制到中间向量，并且响应于具有第二值的相应的第一选择器部分从第三操作数的相应数据字段复制到中间向量。然后，由对应的第二选择器部分索引的中间向量中的数据字段替换目的地的未屏蔽的数据字段。

4. 发明申请

WO2012135429A3 METHOD AND SYSTEM FOR OPTIMIZING PREFETCHING OF CACHE MEMORY LINES 审中-公开
标题翻译：用于优化高速缓存存储器行的前缀的方法和系统
公开(公告)号：WO2012135429A3
公开(公告)日：2012-12-27
申请号：PCT/US2012031093
申请日：2012-03-29
申请人： INTEL CORP , KOU LEIGANG , WIEDEMEIER JEFF , FILIPPO MIKE
发明人： KOU LEIGANG , WIEDEMEIER JEFF , FILIPPO MIKE
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0215 , G06F12/0864 , G06F2212/6026 , G06F2212/6028
摘要： A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.
摘要翻译：一种用于优化处理单元中的高速缓冲存储器线的预取的方法和系统。处理单元具有确定向量存储器操作数是否被缓存在两个或更多个相邻高速缓冲存储器行中的逻辑。在本发明的一个实施例中，矢量存储器操作数是否被缓存在两个或多个相邻高速缓存存储器线中的确定是基于向量存储器操作数的大小和起始地址。在本发明的一个实施例中，使用使用一个问题时隙和一个数据高速缓冲存储器执行时隙的单个指令来执行缓存向量存储器操作数的两个或更多个相邻高速缓存存储器行的预取。通过这样做，当向量存储器操作数被缓存在多于一个高速缓冲存储器行中时，避免了额外的软件预取指令或操作来读取单个向量存储器操作数。

5. 发明申请

WO2012040539A3 FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1S COUNT AND VECTOR PARITY CALCULATION 审中-公开
标题翻译：功能单元，用于向量引导零点，矢量跟踪零，矢量运算1S计数和矢量奇偶计算
公开(公告)号：WO2012040539A3
公开(公告)日：2012-07-05
申请号：PCT/US2011052889
申请日：2011-09-23
申请人： INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER , MAHURIN ERIC W
发明人： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER , MAHURIN ERIC W
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30018
摘要： A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
摘要翻译：描述了在半导体芯片上执行向量操作的方法。该方法包括利用在半导体芯片上实现的矢量功能单元执行第一矢量指令，并用矢量功能单元执行第二矢量指令。第一个向量指令是一个向量乘法加法指令。第二个向量指令是向量前导零计数指令。

6. 发明申请

WO2012040665A3 VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP 审中-公开
标题翻译：在半导体芯片上执行的矢量逻辑减少操作
公开(公告)号：WO2012040665A3
公开(公告)日：2012-07-26
申请号：PCT/US2011053153
申请日：2011-09-24
申请人： INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
发明人： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
IPC分类号： G06F9/305 , G06F1/00 , G06F9/30 , G06F9/44
CPC分类号： G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
摘要翻译：描述半导体处理器。半导体处理器包括执行逻辑减少指令的逻辑电路。逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

7. 发明申请

WO2012040545A3 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
公开(公告)号：WO2012040545A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/052899
申请日：2011-09-23
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

8. 发明申请

WO2012040545A2 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
标题翻译：向量整数倍数加法指令的功能单元
公开(公告)号：WO2012040545A2
公开(公告)日：2012-03-29
申请号：PCT/US2011052899
申请日：2011-09-23
申请人： INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
发明人： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30036
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.
摘要翻译：描述在半导体芯片上实现的用于执行维度N的矢量运算的矢量功能单元。矢量功能单元包括N个功能单元。 N个功能单元中的每一个具有执行以下操作的逻辑电路：第一整数乘加指令，其呈现最高有序位但不是第一整数乘加计算的最低有序位;以及第二整数乘加指令，其呈现最低有序位，但是而不是第二整数乘加计算的最高有序位。

9. 发明申请

WO2014209941A1 PROTECTING INFORMATION PROCESSING SYSTEM SECRETS FROM DEBUG ATTACKS 审中-公开
标题翻译：保护信息处理系统秘密从调查攻击
公开(公告)号：WO2014209941A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/043776
申请日：2014-06-24
申请人： INTEL CORPORATION , SHANBHOGUE, Vedvyas , BRANDT, Jason W. , WIEDEMEIER, Jeff
发明人： SHANBHOGUE, Vedvyas , BRANDT, Jason W. , WIEDEMEIER, Jeff
IPC分类号： G06F21/00 , G06F11/36
CPC分类号： G06F21/62 , G01R31/31719 , G01R31/3177 , G01R31/318588 , G06F11/0727 , G06F11/3656 , G06F21/71 , G06F21/74
摘要： Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.
摘要翻译：公开了一种用于保护信息处理系统秘密免受调试攻击的发明的实施例。在一个实施例中，处理器包括存储器，调试单元和测试访问端口。调试单元将从调试聚合器接收策略。该策略基于第一保险丝的值，具有对应于第一保险丝的生产值的生产模式和对应于保险丝的调试值的调试模式。测试访问端口是使用debug命令在调试模式下提供对存储的访问，并且在生产模式下使用debug命令阻止对存储的访问。

10. 发明申请

WO2012135429A2 METHOD AND SYSTEM FOR OPTIMIZING PREFETCHING OF CACHE MEMORY LINES 审中-公开
标题翻译：用于优化高速缓存存储器线预取的方法和系统
公开(公告)号：WO2012135429A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/031093
申请日：2012-03-29
申请人： INTEL CORPORATION , KOU, Leigang , WIEDEMEIER, Jeff , FILIPPO, Mike
发明人： KOU, Leigang , WIEDEMEIER, Jeff , FILIPPO, Mike
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0215 , G06F12/0864 , G06F2212/6026 , G06F2212/6028
摘要： A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.
摘要翻译：用于优化处理单元中的高速缓冲存储器线的预取的方法和系统。处理单元具有用于确定向量存储器操作数是否被缓存在两个或更多个相邻高速缓存存储器行中的逻辑。在本发明的一个实施例中，确定矢量存储器操作数是否缓存在两个或更多个相邻高速缓存存储器行中是基于矢量存储器操作数的大小和起始地址。在本发明的一个实施例中，使用使用一个发行时隙和一个数据高速缓存存储器执行槽的单个指令来执行缓存向量存储器操作数的两个或更多个相邻高速缓存存储器行的预取。通过这样做，当向量内存操作数被缓存在多个缓存内存行中时，它避免了额外的软件预取指令或操作来读取单个向量内存操作数。

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