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1. 发明申请

WO2014105058A1 OPTIMAL LOGICAL PROCESSOR COUNT AND TYPE SELECTION FOR A GIVEN WORKLOAD ON PLATFORM THERMALS AND POWER BUDGETING CONSTRAINTS 审中-公开
标题翻译：最佳逻辑处理器数量和类型选择平台热量和功率预算限制的工作
公开(公告)号：WO2014105058A1
公开(公告)日：2014-07-03
申请号：PCT/US2012/072135
申请日：2012-12-28
申请人： INTEL CORPORATION , SUBBAREDDY, Dheeraj R. , SRINIVASA, Ganapati N. , KOUFATY, David A. , HAHN, Scott D. , NAIK, Mishali , NARVAEZ, Paolo , PRABHAKARAN, Abirami , GORBATOV, Eugene , NAVEH, Alon , SODHI, Inder M. , WEISSMANN, Eliezer , BRETT, Paul , KHANNA, Gaurav , FENGER, Russell J.
发明人： SUBBAREDDY, Dheeraj R. , SRINIVASA, Ganapati N. , KOUFATY, David A. , HAHN, Scott D. , NAIK, Mishali , NARVAEZ, Paolo , PRABHAKARAN, Abirami , GORBATOV, Eugene , NAVEH, Alon , SODHI, Inder M. , WEISSMANN, Eliezer , BRETT, Paul , KHANNA, Gaurav , FENGER, Russell J.
IPC分类号： G06F9/06 , G06F1/32 , G06F9/46 , G06F9/44
CPC分类号： G06F9/3885 , G06F9/5094 , Y02D10/22
摘要： A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.
摘要翻译：处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于并行执行软件线程的逻辑核心的第二子集。第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

2. 发明申请

WO2014105145A1 HETEROGENEOUS PROCESSOR APPARATUS AND METHOD 审中-公开
标题翻译：异构处理器装置和方法
公开(公告)号：WO2014105145A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046634
申请日：2013-06-19
申请人： INTEL CORPORATION , NARVAEZ, Paolo , SRINIVASA, Ganapati N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David A. , BRETT, Paul , HAHN, Scott D. , HERDRICH, Andrew J. , IYER, Ravishankar , CHITLUR, Nagabhushan , SODHI, Inder M. , KHANNA, Gaurav , FENGER, Russell J.
发明人： NARVAEZ, Paolo , SRINIVASA, Ganapati N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David A. , BRETT, Paul , HAHN, Scott D. , HERDRICH, Andrew J. , IYER, Ravishankar , CHITLUR, Nagabhushan , SODHI, Inder M. , KHANNA, Gaurav , FENGER, Russell J.
IPC分类号： G06F9/28 , G06F9/38 , G06F9/46
CPC分类号： G06F9/5044 , G06F9/45533 , G06F9/5077 , G06F9/5094 , G06F15/80 , Y02D10/22
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行从第一组或第二组物理处理器到第一虚拟处理器。

3. 发明申请

WO2014105174A1 HETEROGENEOUS PROCESSOR APPARATUS AND METHOD 审中-公开
标题翻译：异构处理器装置和方法
公开(公告)号：WO2014105174A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047700
申请日：2013-06-25
申请人： INTEL CORPORATION , NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , KHANNA, Gaurav , FENGER, Russell, J. , BIGBEE, Bryant, E. , HENROID, Andrew, D.
发明人： NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , KHANNA, Gaurav , FENGER, Russell, J. , BIGBEE, Bryant, E. , HENROID, Andrew, D.
IPC分类号： G06F9/44
CPC分类号： G06F9/45558 , G06F9/3885 , G06F9/5077 , G06F2009/4557
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小型物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大型物理处理器核心。

4. 发明申请

WO2014105175A1 HIGH DYNAMIC RANGE SOFTWARE-TRANSPARENT HETEROGENEOUS COMPUTING ELEMENT PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：高动态范围软件 - 透明异构计算元件处理器，方法和系统
公开(公告)号：WO2014105175A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047706
申请日：2013-06-25
申请人： INTEL CORPORATION , GORBATOV, Eugene , NAVEH, Alon , SODHI, Inder M. , SRINIVASA, Ganapati N. , WEISSMANN, Eliezer , KHANNA, Gaurav , NAIK, Mishali , FENGER, Russell J. , HENROID, Andrew D. , SUBBAREDDY, Dheeraj R. , KOUFATY, David A. , NARVAEZ, Paolo
发明人： GORBATOV, Eugene , NAVEH, Alon , SODHI, Inder M. , SRINIVASA, Ganapati N. , WEISSMANN, Eliezer , KHANNA, Gaurav , NAIK, Mishali , FENGER, Russell J. , HENROID, Andrew D. , SUBBAREDDY, Dheeraj R. , KOUFATY, David A. , NARVAEZ, Paolo
IPC分类号： G06F9/28 , G06F9/38 , G06F9/46
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/22
摘要： A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
摘要翻译：一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元素迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下步骤确定是否允许基于评估性能好处。可用的能源和热力预算评估逻辑是评估可用的能源和热预算，并确定如果迁移符合可用能源和热力预算，则允许迁移。工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

5. 发明申请

WO2014105150A1 APPARATUS AND METHOD FOR TRACKING TLB FLUSHES ON A PER THREAD BASIS 审中-公开
标题翻译：在每个螺纹基础上跟踪TLB冲洗的装置和方法
公开(公告)号：WO2014105150A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046907
申请日：2013-06-20
申请人： INTEL CORPORATION , CONRAD, Shaun M. , FENGER, Russell J. , KHANNA, Gaurav , SETH, Rahul , CROSSLAND, James B. , AGGARWAL, Anil
发明人： CONRAD, Shaun M. , FENGER, Russell J. , KHANNA, Gaurav , SETH, Rahul , CROSSLAND, James B. , AGGARWAL, Anil
IPC分类号： G06F9/38 , G06F9/46 , G06F12/10
CPC分类号： G06F12/1027 , G06F1/3206 , G06F2212/683 , Y02D10/13
摘要： A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.
摘要翻译：描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。

6. 发明申请

WO2011034970A1 JUST IN TIME TRUST ESTABLISHMENT AND PROPAGATION 审中-公开
标题翻译：必须在时间信任建立和传播
公开(公告)号：WO2011034970A1
公开(公告)日：2011-03-24
申请号：PCT/US2010/048993
申请日：2010-09-15
申请人： SYMANTEC CORPORATION , CHRISTENSEN, Aaron , BROWNING, William , KHANNA, Gaurav , VADAPALLI, Sreekanth , ANAND, Jatheen
发明人： CHRISTENSEN, Aaron , BROWNING, William , KHANNA, Gaurav , VADAPALLI, Sreekanth , ANAND, Jatheen
IPC分类号： H04L9/32
CPC分类号： H04L9/006 , H04L9/3263
摘要： Trust relationships in an online service system are established at a domain level, and propagated to components of domains as they attempt cross domain communication. In attempting to communicate across domains, a first component in a first domain attempts to validate a certificate of a second component in a second domain. Where the attempt to validate the certificate indicates that a trust relationship does not exist between the first component and the second domain, the first component determines whether a domain level trust relationship exists between the two domains. The first component propagates the trust status between the first and second domains to itself. If there is an existing trust relationship between the first and second domains, the first component validates the certificate of the second component in response. The second component executes the same process to complete the connection.
摘要翻译：在线服务系统中的信任关系建立在域级别，并在域间通信尝试时传播到域的组件。在尝试跨域通信时，第一个域中的第一个组件尝试验证第二个域中的第二个组件的证书。在验证证书的尝试指示第一个组件和第二个域之间不存在信任关系的情况下，第一个组件确定两个域之间是否存在域级别的信任关系。第一个组件将第一个和第二个域之间的信任状态传播给自身。如果第一个域和第二个域之间存在现有的信任关系，则第一个组件验证第二个组件的证书作为响应。第二个组件执行相同的过程来完成连接。

7. 发明申请

WO2018063478A1 ENHANCED POWER MANAGEMENT FOR SUPPORT OF PRIORITY SYSTEM EVENTS 审中-公开
标题翻译：加强电源管理以支持优先系统事件
公开(公告)号：WO2018063478A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/043713
申请日：2017-07-25
申请人： INTEL CORPORATION
发明人： ABOZAED, Muhammad , GORBATOV, Eugene , KHANNA, Gaurav , ANANTHAKRISHNAN, Avinash N.
IPC分类号： G06F1/32 , G06F9/50 , G06F15/78
摘要： Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.
摘要翻译：实施例通常针对用于支持优先系统事件的增强型功率管理。系统的实施例包括处理元件; 存储器，其包括用于关于被指定为优先事件的一个或多个系统事件的信息的注册表; 跟踪要求执行Turbo模式操作的事件操作的机制; 和功率控制单元来实现功率管理算法。该系统将维持第一能量预算和第二剩余能量预算用于在Turbo功率模式下操作，并且其中功率管理算法将基于第二个功率确定是否授权在Turbo功率模式下执行检测到的系统事件在确定第一能量预算不足以执行检测到的系统事件并且检测到的系统事件被指定为优先事件时，剩余能量预算。优先级事件的优先级指定可以包括第一个高优先级指定和第二个重要指定。

8. 发明申请

WO2016204876A1 VIRTUAL MACHINE MANAGEMENT METHOD AND APPARATUS INCLUDING IDLING AND SCHEDULING OF VIRTUAL PROCESSORS 审中-公开
标题翻译：虚拟机管理方法和设备，包括虚拟处理器的定位和调度
公开(公告)号：WO2016204876A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/030801
申请日：2016-05-04
申请人： INTEL CORPORATION
发明人： DHANRAJ, Vijay , KARHU, Abhinav R. , KHANNA, Gaurav , FENGER, Russell J.
IPC分类号： G06F9/455 , G06F9/38 , G06F9/44
CPC分类号： G06F9/50 , G06F9/45558 , G06F9/5027 , G06F9/5077 , G06F2009/4557
摘要： Apparatuses, methods and storage media associated with managing operations of a virtual machine including dynamic idling and scheduling of virtual processors on logical processors described herein. In embodiments, an apparatus may include a physical computing platform with one or more physical processors, a virtual machine manager to manage operation of virtual machines each with a priority level and with one or more virtual processors that operate on logical processor instances of the one or more physical processors, wherein the virtual machine manager tracks activities of the virtual processors that operate on a shared logical processor instance and selectively idles and schedules one or more virtual processors in view of at least the activities of the virtual processors that operate on a shared logical processor instance and the priority of the virtual machines associated with the one or more virtual processors.
摘要翻译：与管理虚拟机的操作相关联的装置，方法和存储介质，包括本文所述的逻辑处理器上的虚拟处理器的动态空闲和调度。在实施例中，装置可以包括具有一个或多个物理处理器的物理计算平台，虚拟机管理器，用于管理各自具有优先级的虚拟机的操作，以及一个或多个虚拟处理器，其在一个或多个物理处理器的逻辑处理器实例上操作更多物理处理器，其中虚拟机管理器跟踪在共享逻辑处理器实例上操作的虚拟处理器的活动，并且考虑到至少在共享逻辑上操作的虚拟处理器的活动，选择性地空闲并调度一个或多个虚拟处理器处理器实例和与一个或多个虚拟处理器相关联的虚拟机的优先级。

9. 发明申请

WO2017171977A1 ENHANCED DIRECTED SYSTEM MANAGEMENT INTERRUPT MECHANISM 审中-公开
标题翻译：增强的直接系统管理中断机制
公开(公告)号：WO2017171977A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/013450
申请日：2017-01-13
申请人： INTEL CORPORATION
发明人： KHANNA, Gaurav , SETHI, Prashant , RAMAMURTHY, Venkatesh
IPC分类号： G06F9/32 , G06F9/48
CPC分类号： G06F13/24
摘要： A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.
摘要翻译：描述了一种方法。该方法包括确定多处理器计算系统中的多个处理器核中的第一处理器核已进入空闲状态，触发用于第一处理器核的SMI，第一处理器核进入系统管理模式（SMM）并且执行一个或更多的平台管理操作。

10. 发明申请

WO2017112149A1 THREAD AND/OR VIRTUAL MACHINE SCHEDULING FOR CORES WITH DIVERSE CAPABILITIES 审中-公开
标题翻译：用于具有不同能力的内核的线程和/或虚拟机调度
公开(公告)号：WO2017112149A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062327
申请日：2016-11-16
申请人： INTEL CORPORATION
发明人： DHANRAJ, Vijay , KHANNA, Gaurav , FENGER, Russell J. , GUPTA, Monica
IPC分类号： G06F9/38 , G06F9/455
CPC分类号： G06F9/5077 , G06F9/45558 , G06F9/5038 , G06F9/5044 , G06F2009/4557 , G06F2009/45591
摘要： Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.
摘要翻译：这里公开了与线程和/或虚拟机的调度相关联的设备，方法和存储介质。在实施例中，设备被提供有操作系统和/或虚拟机监视器的调度器。调度器将以不同的能力检索或接收装置的一个或多个多核处理器的核心的能力，并且至少部分地基于所选择的一个或多个核心中的一个核心来调度多个线程以供执行核的能力和多个线程的特性。至少部分地基于核心的能力和虚拟机的相应优先级，虚拟机监控器将检索或接收核心的能力，并且调度多个虚拟机以便在选定的一个或多个核心上执行。其他实施例可以被描述和/或要求保护。

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