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1. 发明申请

WO2012134558A1 SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION 审中-公开
标题翻译：用于将存储源扩展到目标寄存器并将源地址注册到目标存储器位置的系统，装置和方法
公开(公告)号：WO2012134558A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/064254
申请日：2011-12-09
申请人： INTEL CORPORATION , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , VALENTINE, Robert, C. , DURAN, Santiago, Galan , WIEDEMEIR, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , FORSYTH, Andrew, Thomas , LEE, Victor, W.
发明人： SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , VALENTINE, Robert, C. , DURAN, Santiago, Galan , WIEDEMEIR, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , FORSYTH, Andrew, Thomas , LEE, Victor, W.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30018 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.
摘要翻译：描述了用于在计算机处理器中执行展开和/或压缩指令的系统，装置和方法的实施例。在一些实施例中，扩展指令的执行导致根据写入掩码的值来稀疏地存储在目的地的源的元素的选择，并将源的每个选择的数据元素作为稀疏数据元素存储到目的地位置，其中目的地位置对应于指示要存储源的相应数据元素的每个写入位位置。

2. 发明申请

WO2012134532A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：WO2012134532A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/054303
申请日：2011-09-30
申请人： INTEL CORPORATION , VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
发明人： VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

3. 发明申请

WO2012134560A1 SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK 审中-公开
标题翻译：使用WRITEMASK将两个源操作混合到单个目的地的系统，设备和方法
公开(公告)号：WO2012134560A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/064486
申请日：2011-12-12
申请人： INTEL CORPORATION , SAN ADRIAN, Jesus Corbal , TOLL, Bret L. , VALENTINE, Robert C. , WIEDEMEIER, Jeffrey G. , SAMUDRALA, Sridhar , GIRKAR, Milind Baburao , FORSYTH, Andrew Thomas , OULD-AHMED-VALL, Elmoustapha , BRADFORD, Dennis R. , WU, Lisa K.
发明人： SAN ADRIAN, Jesus Corbal , TOLL, Bret L. , VALENTINE, Robert C. , WIEDEMEIER, Jeffrey G. , SAMUDRALA, Sridhar , GIRKAR, Milind Baburao , FORSYTH, Andrew Thomas , OULD-AHMED-VALL, Elmoustapha , BRADFORD, Dennis R. , WU, Lisa K.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30192 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.
摘要翻译：描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的数据元素到达目的地的目标位置。

4. 发明申请

WO2012040665A2 VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP 审中-公开
标题翻译：在半导体芯片上实现的矢量逻辑减少操作
公开(公告)号：WO2012040665A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053153
申请日：2011-09-24
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
IPC分类号： G06F9/305 , G06F9/30 , G06F9/44 , G06F1/00
CPC分类号： G06F9/30029 , G06F7/00 , G06F9/06 , G06F9/30032 , G06F9/30036 , G06F15/76
摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
摘要翻译：描述半导体处理器。该半导体处理器包括执行逻辑缩减指令的逻辑电路。逻辑电路具有混合电路以搅拌矢量的元素以形成混合矢量。逻辑电路还具有矢量逻辑电路，以对所述矢量和所述调配矢量执行矢量逻辑运算。

5. 发明申请

WO2012040545A3 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
公开(公告)号：WO2012040545A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/052899
申请日：2011-09-23
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

6. 发明申请

WO2014004220A1 DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 审中-公开
标题翻译：双重圆形组合浮点数乘法和加法
公开(公告)号：WO2014004220A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046619
申请日：2013-06-19
申请人： INTEL CORPORATION , SAMUDRALA, Sridhar , MAGKLIS, Grigorios , LUPON, Marc , DITZEL, David R.
发明人： SAMUDRALA, Sridhar , MAGKLIS, Grigorios , LUPON, Marc , DITZEL, David R.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
摘要翻译：公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数，基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。分别使用溢出检测选择最终结果。

7. 发明申请

WO2013101119A1 METHOD AND APPARATUS FOR CONTROLLING A MXCSR 审中-公开
标题翻译：用于控制MXCSR的方法和装置
公开(公告)号：WO2013101119A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067957
申请日：2011-12-29
申请人： INTEL CORPORATION , MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
IPC分类号： G06F15/76 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.
摘要翻译：公开了一种通常涉及控制多媒体扩展控制和状态寄存器（MXCSR）的装置和方法。处理器核心可以包括用于执行算术功能的浮点单元（FPU）以及为FPU提供控制位的多媒体扩展控制寄存器（MXCR）。此外，优化器可以用于从多个SPEC_MXSR中选择推测性多媒体扩展状态寄存器（SPEC_MXSR），以基于指令来更新多媒体扩展状态寄存器（MXSR）。

8. 发明申请

WO2012040539A2 FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1S COUNT AND VECTOR PARITY CALCULATION 审中-公开
标题翻译：功能单元，用于向量主导零点，向量跟踪零点，向量运算符1S计数和向量奇异值计算
公开(公告)号：WO2012040539A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/052889
申请日：2011-09-23
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger , MAHURIN, Eric, W.
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger , MAHURIN, Eric, W.
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30018
摘要： A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
摘要翻译：描述了对半导体芯片执行矢量操作的方法。该方法包括利用在半导体芯片上实现的向量功能单元执行第一向量指令并且利用向量功能单元执行第二向量指令。第一个向量指令是一个向量乘加指令。第二个向量指令是一个向量前导零计数指令。

9. 发明申请

WO2022271239A1 QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD 审中-公开
公开(公告)号：WO2022271239A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/021809
申请日：2022-03-24
申请人： INTEL CORPORATION
发明人： VASUDEVAN, Anil , SAMUDRALA, Sridhar , PATIL, Kiran , NAMBIAR, Amritha , SARANGAM, Parthasarathy
IPC分类号： G06F9/48 , G06F9/52 , G06F2209/5018 , G06F9/4881 , G06F9/5083 , G06F9/526
摘要： Examples described herein relate to one or more processors that execute a number of polling threads based on a number of queue identifiers, wherein at least one of the queue identifiers is associated with one or more queues. In some examples, the one or more processors selectively adjust a number of queue identifiers based on a load level of a queue. In some examples, the load level of a queue indicates a number of packets processed per unit of time. In some examples, the number of queue identifiers is no more than a number of configured queues. In some examples, the one or more queues are associated with a queue exclusively allocated to a thread for reading or writing.

10. 发明申请

WO2022125211A1 TECHNOLOGIES THAT PROVIDE POLICY ENFORCEMENT FOR RESOURCE ACCESS 审中-公开
公开(公告)号：WO2022125211A1
公开(公告)日：2022-06-16
申请号：PCT/US2021/057130
申请日：2021-10-28
申请人： INTEL CORPORATION [US]/[US]
发明人： JAIN, Anjali Singhai , DALY, Daniel , SAMUDRALA, Sridhar , CORNETT, Linden , BURRA, Phani , CREELEY, Brett
IPC分类号： H04L41/00 , G06F9/455
摘要： Examples described herein relate to one or more processors, when operational, to execute instructions stored in memory device, to cause performance of: execute a driver that is to: negotiate capabilities of hardware with a control plane for a virtualized execution environment and limit capabilities of the hardware available to the virtualized execution environment based on a service level agreement (SLA) associated with the virtualized execution environment. In some examples, the driver is to advertise hardware capabilities requested by the virtualized execution environment. In some examples, the control plane is to set capabilities of a hardware available to the virtualized execution environment based on the SLA.

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