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1. 发明申请

WO2005091147A1 A CACHE MECHANISM 审中-公开
标题翻译：高速缓存机制
公开(公告)号：WO2005091147A1
公开(公告)日：2005-09-29
申请号：PCT/US2005/008337
申请日：2005-03-14
申请人： INTEL CORPORATION , RAKVIC, Ryan , WU, Youfeng , BLACK, Bryan , SHEN, John
发明人： RAKVIC, Ryan , WU, Youfeng , BLACK, Bryan , SHEN, John
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0888
摘要： According to one embodiment a system is disclosed. The system includes a cent al processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
摘要翻译：根据一个实施例，公开了一种系统。该系统包括中央处理单元（CPU），第一高速缓存存储器，其耦合到CPU以仅存储要在CPU处理的重要负载的数据;耦合到CPU的第二高速缓存存储器，用于存储半数据在CPU处理的负载，以及耦合到CPU，第一高速缓冲存储器和第二高速缓冲存储器的第三高速缓存存储器，用于存储在CPU处理的非重要负载。

2. 发明申请

WO2005013118A2 RENAMING FOR REGISTER WITH MULTIPLE BIT FIELDS 审中-公开
标题翻译：为多个位的寄存器注册
公开(公告)号：WO2005013118A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/023235
申请日：2004-07-16
申请人： INTEL CORPORATION , RUPLEY, Jeffrey, II , BREKELBAUM, Edward , BLACK, Bryan
发明人： RUPLEY, Jeffrey, II , BREKELBAUM, Edward , BLACK, Bryan
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/384
摘要： An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.
摘要翻译：提供了一种装置和方法，用于重新命名允许不同长度的位访问的逻辑寄存器，例如谓词寄存器。重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。重命名逻辑使用与逻辑寄存器相关联的重命名映射表被重命名，并且还包括多个物理重命名寄存器。它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。还可以使用附加大小的物理重命名寄存器。单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。

3. 发明申请

WO2005062190A1 MULTI-DIE PROCESSOR 审中-公开
标题翻译：多加工机
公开(公告)号：WO2005062190A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/039236
申请日：2004-11-24
申请人： INTEL CORPORATION , BLACK, Bryan , SAMRA, Nicholas , WEBB, M., Clair
发明人： BLACK, Bryan , SAMRA, Nicholas , WEBB, M., Clair
IPC分类号： G06F15/78
CPC分类号： G06F15/7832 , H01L24/16 , H01L25/0657 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06562 , H01L2225/06565 , H01L2924/00013 , H01L2924/14 , Y02D10/12 , Y02D10/13 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00 , H01L2924/00014
摘要： Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.
摘要翻译：公开了一种多芯片处理器装置和系统。执行一个或多个指令的处理器逻辑在两个或多个面对面堆叠的骰子之间分配。处理器包括在堆叠的骰子之间的导电接口，以便于管芯到管芯的通信。

4. 发明申请

WO2008079625A1 METHOD FOR INCORPORATING EXISTING SILICON DIE INTO 3D INTEGRATED STACK 审中-公开
标题翻译：将现有硅芯片并入3D集成堆叠的方法
公开(公告)号：WO2008079625A1
公开(公告)日：2008-07-03
申请号：PCT/US2007/086674
申请日：2007-12-06
申请人： INTEL CORPORATION , REED, Paul , BLACK, Bryan
发明人： REED, Paul , BLACK, Bryan
IPC分类号： H01L23/12
CPC分类号： H01L25/0652 , H01L23/481 , H01L25/18 , H01L2224/0401 , H01L2224/06156 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.
摘要翻译：一种包括包括多个导电通过基板通孔（TSV））的第一管芯的装置; 以及多个第二骰子，每个第二骰子都包括耦合到第一骰子的TSV的多个接触点，所述多个第二骰子被布置成集体地包括接近第一骰子的表面积的表面积。一种方法，包括在第一管芯上布置多个第二管芯，使得多个第二管芯集体包括接近第一管芯表面积的表面积; 以及将多个第二装置电耦合到多个第一管芯。一种包括包括印刷电路板和模块的电子设备的系统，所述模块包括包括多个TSV的第一裸片; 并且所述多个第二管芯被布置成共同地包括接近所述第一管芯的表面积的表面积。

5. 发明申请

WO2012040274A1 SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS 审中-公开
标题翻译：半导体芯片通过加强硅 - 六面体
公开(公告)号：WO2012040274A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052469
申请日：2011-09-21
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , SU, Michael, Z. , REFAI-AHMED, Gamal , BLACK, Bryan
发明人： SU, Michael, Z. , REFAI-AHMED, Gamal , BLACK, Bryan
IPC分类号： H01L23/58 , H01L23/60 , H01L25/065 , H01L23/00
CPC分类号： H01L23/585 , H01L21/76898 , H01L23/3171 , H01L23/481 , H01L23/49816 , H01L23/60 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/81 , H01L2924/00
摘要： A method of manufacturing includes connecting a first end (131) of a first through-silicon- via (100f) to a first die seal (125) proximate a first side of a first semiconductor chip (15). A second end (133) of the first thu-silicon-via is connected to a second die seal (115) proximate a second side of the first semiconductor chip opposite the first side.
摘要翻译：一种制造方法包括将第一穿硅通孔（100f）的第一端（131）连接到靠近第一半导体芯片（15）的第一侧的第一模具密封件（125）。第一硅硅通孔的第二端（133）连接到靠近第一半导体芯片的与第一侧相对的第二侧的第二模具密封件（115）。

6. 发明申请

WO2012034064A1 SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL 审中-公开
标题翻译：半导体芯片设备
公开(公告)号：WO2012034064A1
公开(公告)日：2012-03-15
申请号：PCT/US2011/051075
申请日：2011-09-09
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , SU, Michael, Z. , FU, Lei , REFAI-AHMED, Gamal , BLACK, Bryan
发明人： SU, Michael, Z. , FU, Lei , REFAI-AHMED, Gamal , BLACK, Bryan
IPC分类号： H01L21/56
CPC分类号： H01L21/563 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/50 , H01L2224/13025 , H01L2224/16146 , H01L2224/16235 , H01L2224/17181 , H01L2224/26145 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125 , H01L2224/94 , H01L2924/10252 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15159 , H01L2924/15311 , H01L2224/16225 , H01L2924/00 , H01L2224/81
摘要： A method of manufacturing is provided that includes placing a removable cover (195, 195 ', 195 ") on a surface (215) of a substrate (120). The substrate includes a first semiconductor chip (1 10) positioned on the surface. The first semiconductor chip includes a first sidewall (170). The removable cover includes a second sidewall (200) positioned opposite the first sidewall. A first underfill (155) is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed.
摘要翻译：提供了一种制造方法，其包括将可移除的盖子（195,195'，195“）放置在基板（120）的表面（215）上。该基板包括位于表面上的第一半导体芯片（110）。第一半导体芯片包括第一侧壁（170），可移除的盖包括与第一侧壁相对设置的第二侧壁（200），第一底部填充物（155）被放置在第一半导体芯片和表面之间，其中第二侧壁提供第一底部填充物的流动障碍。还公开了各种装置。

7. 发明申请

WO2010107542A1 THERMAL INTERFACE MATERIAL WITH SUPPORT STRUCTURE 审中-公开
标题翻译：具有支撑结构的热界面材料
公开(公告)号：WO2010107542A1
公开(公告)日：2010-09-23
申请号：PCT/US2010/024589
申请日：2010-02-18
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , TOUZELBAEV, Maxat , BLACK, Bryan , YANG, Yizhang , REFAI-AHMED, Gamal
发明人： TOUZELBAEV, Maxat , BLACK, Bryan , YANG, Yizhang , REFAI-AHMED, Gamal
IPC分类号： H01L23/42
CPC分类号： H01L23/42 , H01L2224/0554 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/13025 , H01L2224/16225 , H01L2224/29076 , H01L2224/29109 , H01L2224/29111 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29169 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2924/01047 , H01L2924/013 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip (15, 115) and a heat spreader (30) is provided. The method includes placing a thermal interface material layer (35, 35 ', 35 ", 35 " ', 35 " ") containing a support structure (40, 40') on the first semiconductor chip (15, 115). The heat spreader (30) is positioned proximate the thermal interface material layer (35, 35 ', 35 ", 35 " ', 35 " "). The thermal interface material layer (35, 35 ', 35 ", 35 " ', 35 "") is reflowed to establish thermal contact with both the first semiconductor chip (15, 115) and the heat spreader (30).
摘要翻译：公开了各种半导体芯片热界面材料的方法和装置。一方面，提供了在第一半导体芯片（15,115）和散热器（30）之间建立热接触的方法。该方法包括将包含支撑结构（40,40'）的热界面材料层（35,35'，35“，35”'，35“）放置在第一半导体芯片（15,115）上。散热器（30）位于热界面材料层（35,35'，35“，35”'，35“”）附近。热界面材料层（35,35'，35“，35”'，35“”）被回流以与第一半导体芯片（15,115）和散热器（30）建立热接触。

8. 发明申请

WO2018165659A1 SYSTEM AND METHOD FOR RAPIDLY ACCESSING AN IMPROVED TOURNIQUET 审中-公开
公开(公告)号：WO2018165659A1
公开(公告)日：2018-09-13
申请号：PCT/US2018/021999
申请日：2018-03-12
申请人： BLACK, Bryan
发明人： BLACK, Bryan
IPC分类号： A61B17/00 , A61B17/132
CPC分类号： A61B17/1322 , A45F5/021 , A45F2200/0566 , A61B17/1327 , A61B50/00 , A61B50/20 , A61B2050/005 , A61B2050/0051 , A61B2050/0085 , A61B2050/314
摘要： A system and method for rapidly accessing a tourniquet located in a pouch with a pull-away cover. The tourniquet holder allows users to safely store in a fabric pouch a prepared tourniquet that is quickly accessible and coupled to a removable cover of the pouch. Users are able to fold tourniquet in a manner that allow the tourniquet to be removed from the pouch and used nearly instantaneously.

9. 发明申请

WO2012040271A1 STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT 审中-公开
标题翻译：具有热管理的堆叠半导体芯片器件
公开(公告)号：WO2012040271A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052466
申请日：2011-09-21
申请人： ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC. , REFAI-AHMED, Gamal , BLACK, Bryan , SU, Michael, Z.
发明人： REFAI-AHMED, Gamal , BLACK, Bryan , SU, Michael, Z.
IPC分类号： H01L25/065 , H01L23/36
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/42 , H01L23/49816 , H01L23/49827 , H01L25/0652 , H01L2023/4062 , H01L2224/1403 , H01L2224/141 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32245 , H01L2224/73253 , H01L2224/81192 , H01L2224/83192 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/01322 , H01L2924/15151 , H01L2924/15311 , H01L2924/15321 , H05K1/0204 , H05K1/141 , H05K1/181 , H05K2201/09072 , H05K2201/10378 , H05K2201/10416 , H05K2201/10515 , H05K2201/1056
摘要： A method of manufacturing is provided that includes placing a thermal management device (75) in thermal contact with a first semiconductor chip (35) of a semiconductor chip device (10). The semiconductor chip device includes a first substrate (60) coupled to the first semiconductor chip. The first substrate has a first aperture (70). At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.
摘要翻译：提供一种制造方法，其包括将热管理装置（75）放置成与半导体芯片装置（10）的第一半导体芯片（35）热接触。半导体芯片器件包括耦合到第一半导体芯片的第一衬底（60）。第一基板具有第一孔（70）。第一半导体芯片和热管理装置中的至少一个至少部分地位于第一孔中。

10. 发明申请

WO2012105967A1 ASSET MANAGEMENT ARCHITECTURE FOR CONTENT DELIVERY NETWORKS 审中-公开
标题翻译：内容交付网络资产管理架构
公开(公告)号：WO2012105967A1
公开(公告)日：2012-08-09
申请号：PCT/US2011/023410
申请日：2011-02-01
申请人： LIMELIGHT NETWORKS, INC. , DUNBAR, Neil , BOELENS, Jared , BLACK, Bryan , LANGE, Sig , KNOL, Luke , ROERSMA, Jacob, S.
发明人： DUNBAR, Neil , BOELENS, Jared , BLACK, Bryan , LANGE, Sig , KNOL, Luke , ROERSMA, Jacob, S.
IPC分类号： G06F15/16 , G06F9/06 , G06F17/30
CPC分类号： H04L67/1002 , H04L67/1097
摘要： A method and system for flexibly processing content objects is disclosed. The processing is performed with a content delivery network (CDN) having a number of geographically distributed points of presence (POPs). Content objects are ingest through landing pads and stored or otherwise processed in a flexible way where storage bricks and other resources are chosen flexibly by characterization tags. Policies are used to describe which content objects are processed by which categories of resources. A group of resources characterized by the tag are chosen when the processing is performed. When retrieving content, the content object can be stored on any storage brick found through the tag analysis process. A query is translated to addresses for the chosen storage brick(s).
摘要翻译：公开了一种用于灵活处理内容对象的方法和系统。使用具有多个地理上分布的存在点（POP）的内容递送网络（CDN）来执行处理。内容对象通过着陆垫进行摄取，并以灵活的方式进行存储或以其他方式处理，其中通过表征标签灵活地选择存储砖和其他资源。策略用于描述哪些内容对象由哪些类别的资源处理。当执行处理时，选择由标签表征的一组资源。检索内容时，内容对象可以存储在通过标签分析过程找到的任何存储砖上。查询将转换为所选存储砖的地址。

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