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1. 发明申请

WO2013101158A1 METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) 审中-公开
标题翻译：元数据管理和支持相位变化记忆与开关（PCMS）
公开(公告)号：WO2013101158A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068040
申请日：2011-12-30
申请人： INTEL CORPORATION , PUTHIYEDATH, Leena, K. , JONES, Marc, T. , TETRICK, Scott, R. , ROYER, Robert, J., Jr. , RAMANUJAN, Raj, K. , HINTON, Glenn, J. , FANNING, Blaise , GITTINS, Robert, S. , SCHMISSEUR, Mark, A. , HADY, Frank, T. , FABER, Robert, W.
发明人： PUTHIYEDATH, Leena, K. , JONES, Marc, T. , TETRICK, Scott, R. , ROYER, Robert, J., Jr. , RAMANUJAN, Raj, K. , HINTON, Glenn, J. , FANNING, Blaise , GITTINS, Robert, S. , SCHMISSEUR, Mark, A. , HADY, Frank, T. , FABER, Robert, W.
IPC分类号： G06F12/00 , G06F13/14 , G06F11/08 , G11C13/02
CPC分类号： G11C16/3431 , G06F11/1048 , G06F12/0246 , G11C13/0004 , G11C14/0045
摘要： Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与用于PCMS（带有交换机的相变存储器））元件的管理和/或支持相关的方法和装置。在一个实施例中，PCMS控制器允许基于元数据访问PCMS设备。可以使用元数据来提供如本公开中所讨论的效率，耐久性，纠错等。还公开并要求保护其他实施例。

2. 发明申请

WO2013048490A1 NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) AS A REPLACEMENT FOR TRADITIONAL MASS STORAGE 审中-公开
标题翻译：非易失性随机存取存储器（NVRAM）作为传统存储的替代
公开(公告)号：WO2013048490A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054414
申请日：2011-09-30
申请人： INTEL CORPORATION , PUTHIYEDATH, Leena, K. , FANNING, Blaise , OPFERMAN, Tony , CROSSLAND, James, B.
发明人： PUTHIYEDATH, Leena, K. , FANNING, Blaise , OPFERMAN, Tony , CROSSLAND, James, B.
IPC分类号： G06F12/00 , G06F13/14 , G06F13/16
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte -rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。计算机系统包括执行软件的处理器和耦合到处理器的存储器。存储器的至少一部分包括由处理器字节可刷新和字节可擦除的非易失性随机存取存储器（NVRAM）。该系统还包括耦合到NVRAM的存储器控制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

3. 发明申请

WO2013101050A1 MULTI-LEVEL MEMORY WITH DIRECT ACCESS 审中-公开
标题翻译：具有直接访问的多级记忆
公开(公告)号：WO2013101050A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067824
申请日：2011-12-29
申请人： INTEL CORPORATION , FANNING, Blaise , QAWAMI, Shekoufeh , TETRICK, Raymond S. , HADY, Frank T.
发明人： FANNING, Blaise , QAWAMI, Shekoufeh , TETRICK, Raymond S. , HADY, Frank T.
IPC分类号： G06F12/00 , G11C13/02 , G11C16/00
CPC分类号： G06F3/0644 , G06F3/0604 , G06F3/0631 , G06F3/0679 , G06F3/0688 , G06F12/023 , G06F12/0238 , G06F12/0246 , G06F12/08 , G06F12/10 , G06F12/1009 , G06F2212/2024 , G06F2212/205 , G06F2212/7201 , G06F2212/7204 , G11C7/1006 , G11C11/56 , G11C16/00 , Y02D10/13
摘要： Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
摘要翻译：公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

4. 发明申请

WO2014099025A1 TECHNIQUES TO CONFIGURE A SOLID STATE DRIVE TO OPERATE IN A STORAGE MODE OR A MEMORY MODE 审中-公开
标题翻译：配置固态驱动器在存储模式或存储器模式下运行的技术
公开(公告)号：WO2014099025A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048414
申请日：2013-06-28
申请人： INTEL CORPORATION , FANNING, Blaise , SCHMISSEUR, Mark, A. , TETRICK, Raymond, S. , ROYER, Robert, J. , MINTURN, David, B. , MATTHEWS, Shane
发明人： FANNING, Blaise , SCHMISSEUR, Mark, A. , TETRICK, Raymond, S. , ROYER, Robert, J. , MINTURN, David, B. , MATTHEWS, Shane
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0632 , G06F3/0634 , G06F3/0644 , G06F3/0664 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F13/16 , G06F13/28 , G06F2212/7206
摘要： Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
摘要翻译：公开了用于配置固态驱动器（SSD）以在存储模式或存储器模式下操作的示例。在一些示例中，可以在具有一个或多个非易失性存储器阵列的SSD的控制器处接收一个或多个配置命令。 SSD可以被配置为基于一个或多个配置命令以存储模式，存储模式或者存储模式或存储器模式的组合中的至少一个进行操作。其他的例子被描述和要求保护。

5. 发明申请

WO2014163880A1 MEMORY LATENCY MANAGEMENT 审中-公开
标题翻译：内存管理
公开(公告)号：WO2014163880A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/018513
申请日：2014-02-26
申请人： INTEL CORPORATION , ROYER, JR., Robert J. , FANNING, Blaise , OOI, Eng Hun
发明人： ROYER, JR., Robert J. , FANNING, Blaise , OOI, Eng Hun
IPC分类号： G06F13/14 , G06F12/00 , G06F11/10
CPC分类号： G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于管理存储器延迟操作的装置，系统和方法。在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控制逻辑，将数据存储在本地高速缓冲存储器中，接收与该数据相关联的纠错码指示符，并实现数据管理策略响应于纠错码指示器。还公开并要求保护其他实施例。

6. 发明申请

WO2013101053A1 NON-VOLATILE RAM DISK 审中-公开
标题翻译：非易失性RAM盘
公开(公告)号：WO2013101053A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067829
申请日：2011-12-29
申请人： INTEL CORPORATION , CROSSLAND, James B. , OPFERMAN, Toby , FANNING, Blaise
发明人： CROSSLAND, James B. , OPFERMAN, Toby , FANNING, Blaise
IPC分类号： G06F12/02 , G06F13/16 , G11C13/02
CPC分类号： G06F12/0638 , G06F12/023 , G06F12/0238 , G06F12/0866 , G06F2212/202 , G06F2212/2024 , G06F2212/205 , G11C7/1072 , G11C13/0004 , G11C14/0036 , G11C14/0045
摘要： A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.
摘要翻译：公开了一种方法和系统。在一个实施例中，该方法包括在相变存储器和交换机（PCMS）存储器内分配若干存储器位置，以用作随机存取存储器（RAM）盘。 RAM磁盘创建为由计算机系统中运行的软件应用程序使用。该方法还包括将分配的PCMS存储器的至少一部分映射到软件应用地址空间。最后，该方法还允许软件应用直接访问PCMS存储器的分配量的至少一部分。

7. 发明申请

WO2006066182A1 MEDIA PLAYER WITH HIGH-RESOLUTION AND LOW-RESOLUTION IMAGE FRAME BUFFERS 审中-公开
标题翻译：具有高分辨率和低分辨率图像帧缓冲器的媒体播放器
公开(公告)号：WO2006066182A1
公开(公告)日：2006-06-22
申请号：PCT/US2005/045879
申请日：2005-12-13
申请人： INTEL CORPORATION , FANNING, Blaise
发明人： FANNING, Blaise
IPC分类号： H04N7/24 , H04N7/64 , H04N7/26
CPC分类号： H04N21/4621 , H04N19/423 , H04N19/59 , H04N19/89 , H04N21/23439 , H04N21/44004
摘要： According to some embodiments, a low-resolution buffer may be provided to store lower-resolution image frame information associated with first media content. A high-resolution buffer may also be provided to store higher-resolution image frame information also associated with the first media content. A playback device may then receive (i) the higher-resolution image frame information if the higher-resolution image frame information is available or (ii) the lower-resolution image frame information if the higher-resolution image frame information is not available.
摘要翻译：根据一些实施例，可以提供低分辨率缓冲器来存储与第一媒体内容相关联的较低分辨率图像帧信息。还可以提供高分辨率缓冲器来存储也与第一媒体内容相关联的更高分辨率的图像帧信息。如果较高分辨率图像帧信息可用，则再现设备可以接收（i）较高分辨率图像帧信息，或者如果较高分辨率图像帧信息不可用，则可以接收较低分辨率图像帧信息。

8. 发明申请

WO2013048536A1 APPARATUS AND METHOD FOR MANAGING REGISTER INFORMATION IN A PROCESSING SYSTEM 审中-公开
标题翻译：在处理系统中管理寄存器信息的装置和方法
公开(公告)号：WO2013048536A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054496
申请日：2011-10-01
申请人： INTEL CORPORATION , FANNING, Blaise , SABBAVARAPU, Anil K.
发明人： FANNING, Blaise , SABBAVARAPU, Anil K.
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305 , G06F13/16
CPC分类号： G06F9/44505 , G06F11/1441 , Y02D10/43
摘要： The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.
摘要翻译：配置寄存器中的设置基于存储在管理寄存器中的值和/或基于在调试操作期间产生复位信号或检测电子系统中的故障或功率状态转换来控制。管理寄存器可以向每个配置寄存器分配一个位，并且将根据该位的值来控制要加载到配置寄存器中的设置。另外或替代地，当复位信号呈现指示要存储默认设置的值时，可以控制配置寄存器中的设置。

9. 发明申请

WO2013100909A1 ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的自适应配置
公开(公告)号：WO2013100909A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067407
申请日：2011-12-27
申请人： INTEL CORPORATION , QAWAMI, Shekoufeh , SUNDARAM, Rajesh , ZIMMERMAN, David J. , FANNING, Blaise
发明人： QAWAMI, Shekoufeh , SUNDARAM, Rajesh , ZIMMERMAN, David J. , FANNING, Blaise
IPC分类号： G11C16/06 , G11C13/02 , G06F12/00 , G06F9/06
CPC分类号： G11C13/0038 , G06F1/3275 , G06F9/30101 , G06F12/0246 , G11C13/0004 , G11C13/0033 , G11C16/06 , Y02D10/14
摘要： Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要翻译：公开了用于非易失性存储器的自适应配置的示例。示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。

10. 发明申请

WO2008083012A1 EFFICIENT POWER MANAGEMENT TECHNIQUES FOR COMPUTER SYSTEMS 审中-公开
标题翻译：计算机系统的高效电源管理技术
公开(公告)号：WO2008083012A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088240
申请日：2007-12-19
申请人： INTEL CORPORATION , FANNING, Blaise
发明人： FANNING, Blaise
IPC分类号： G06F13/00 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a control module. The interface communicates with the processor regarding power states of the processor. The control module may initiate draining the IOQ upon a commencement of a power state transition for the processor. The control module allows the transition of the processor to continue during the draining of the IOQ. However, at a particular point in the transition, the control module may determine whether the IOQ is empty. If so, then the control module may allow the transition of the processor to continue. Otherwise, the control module may stop the transition of the processor until the IOQ is empty.
摘要翻译：公开了涉及计算机系统中的电力管理技术的技术。例如，设备可以包括输入输出队列（IOQ），耦合到处理器的接口和控制模块。接口与处理器通信处理器的电源状态。控制模块可以在处理器的功率状态转换开始时启动排出IOQ。控制模块允许处理器在IOQ排水期间继续进行。然而，在转换中的特定点处，控制模块可以确定IOQ是否为空。如果是这样，则控制模块可以允许处理器的转换继续。否则，控制模块可能会停止处理器的转换，直到IOQ为空。

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