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1. 发明申请

WO2013081587A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供向量水平主要投票功能
公开(公告)号：WO2013081587A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062487
申请日：2011-11-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , KSHITIJ, Doshi A. , SAIR, Suleyman , YOUNT, Charles R.
发明人： OULD-AHMED-VALL, Elmoustapha , KSHITIJ, Doshi A. , SAIR, Suleyman , YOUNT, Charles R.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
摘要： Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要翻译：指令和逻辑提供向量横向多数投票功能。一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数从源操作数的数据字段数读取的值。

2. 发明申请

WO2013081588A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供矢量水平比较功能
公开(公告)号：WO2013081588A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062488
申请日：2011-11-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , SAIR, Suleyman , KSHITIJ, Doshi A.
发明人： OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , SAIR, Suleyman , KSHITIJ, Doshi A.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30145 , G06F7/02 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
摘要翻译：指令和逻辑提供向量横向比较功能。一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取值，对应于掩码，并比较相等的值。在一些实施例中，响应于不等式的检测，可以采取陷阱。在一些替代实施例中，可以设置标志。在其他替代实施例中，可以将掩模字段设置为对应不等值的掩蔽状态。在一些实施例中，响应于源操作数的所有未屏蔽的数据字段等于特定值，该值可以广播到目的地操作数中指定大小的所有数据字段。

3. 发明申请

WO2013048367A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY 审中-公开
标题翻译：指导和逻辑提供矢量负载和存储条以及屏蔽功能
公开(公告)号：WO2013048367A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/053321
申请日：2011-09-26
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , DOSHI, Kshitij A. , SAIR, Suleyman , YOUNT, Charles R.
发明人： OULD-AHMED-VALL, Elmoustapha , DOSHI, Kshitij A. , SAIR, Suleyman , YOUNT, Charles R.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.
摘要翻译：指令和逻辑提供具有跨度和掩码功能的矢量加载和/或存储。一些实施例响应于指定以下内容的指令：一组加载，目的寄存器，掩码寄存器，存储器地址和步长; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的步长倍数。第一个掩码值指示该元素尚未从内存加载，第二个值指示该元素不需要或已经加载。对于具有第一值的每一个，根据掩码寄存器中的数据字段的位置生成所述步长的对应倍数，以将数据元素从存储器加载到对应的目的地寄存器位置，并且掩码寄存器中的对应值被改变到第二个值。这些说明可以在故障后重新启动。

4. 发明申请

WO2013101227A1 VECTOR FREQUENCY COMPRESS INSTRUCTION 审中-公开
标题翻译：矢量频率压缩指令
公开(公告)号：WO2013101227A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068230
申请日：2011-12-30
申请人： INTEL CORPORATION , SAIR, Suleyman , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , DOSHI, Kshitij A. , TOLL, Bret L.
发明人： SAIR, Suleyman , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , DOSHI, Kshitij A. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/3016 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要翻译：一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。目标操作数标识目标向量寄存器。处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定的压缩值，后跟该运行的运行长度。

5. 发明申请

WO2013101223A1 EFFICIENT ZERO-BASED DECOMPRESSION 审中-公开
标题翻译：高效的基于零的分解
公开(公告)号：WO2013101223A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068226
申请日：2011-12-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译：一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。第二个掩码基于尾随零的计数。执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。将缓冲区移位并复制到结果，并将源数据元素集合向右移动。如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。

6. 发明申请

WO2013101218A1 VECTOR FREQUENCY EXPAND INSTRUCTION 审中-公开
标题翻译：矢量频率扩展指令
公开(公告)号：WO2013101218A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068217
申请日：2011-12-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30025 , G06F9/30036 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要翻译：包括硬件解码单元和执行引擎单元的处理器核心。所述硬件解码单元对矢量频率扩展指令进行解码，其中所述向量频率压缩指令包括源操作数和目的操作数，其中所述源操作数指定源向量寄存器，所述源向量寄存器包括一对或多对值和游程长度，根据运行长度将其扩展为该值的运行。执行引擎单元，用于执行解码矢量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及包括在源向量寄存器中运行长度编码的至少一个相同值的运行。

7. 发明申请

WO2017112246A1 INSTRUCTIONS AND LOGIC FOR LOAD-INDICES-AND-GATHER OPERATIONS 审中-公开
标题翻译：指标和逻辑负载指数和收集操作
公开(公告)号：WO2017112246A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063297
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： YOUNT, Charles R. , GOKHALE, Indraneil M. , VALLES, Antonio C. , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/3016 , G06F12/0862 , G06F12/0875 , G06F2212/1016 , G06F2212/452 , G06F2212/6028
摘要： A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.
摘要翻译：处理器包括执行单元以执行指令以加载来自索引阵列的索引，并基于这些索引从稀疏存储器中的随机位置或位置收集元素。执行单元包括用于根据需要为指令要采集的每个数据元素加载要用于计算要采集的特定数据元素的存储器中的地址的索引值的逻辑。索引值可以从为该指令识别的索引数组中检索。执行单元包括用于计算地址的逻辑，该地址是为指令指定的基地址和为数据元素检索的索引值之和，具有或不具有缩放比例。执行单元包括将收集的数据元素存储在为指令指定的目的地向量寄存器中的连续位置中的逻辑。

8. 发明申请

WO2017112175A1 INSTRUCTIONS AND LOGIC FOR LOAD-INDICES-AND-SCATTER OPERATIONS 审中-公开
标题翻译：负载指数和散射操作的指令和逻辑
公开(公告)号：WO2017112175A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062705
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： GOKHALE, Indraneil M. , YOUNT, Charles R. , VALLES, Antonio C. , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/44 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30101 , G06F9/3016 , G06F12/084 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/1027 , G06F2212/452
摘要： A processor includes an execution unit to execute instructions to load indices from an array of indices and scatter elements to locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be scattered by the instruction, as needed, an index value to be used in computing the address in memory at which a particular data element is to be written. The index values may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction and the index values retrieved for the data element locations, with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction and store them to the computed locations.
摘要翻译：处理器包括执行单元以执行指令以从指数阵列加载指数并基于这些指数将元素散布到稀疏存储器中的位置。执行单元包括用于对于要由指令散布的每个数据元素根据需要加载用于计算存储器中的地址的索引值的逻辑，在该地址处将写入特定的数据元素。索引值可以从为该指令识别的索引数组中检索。执行单元包括用于基于为指令指定的基地址和为数据元素位置检索的索引值的总和来计算地址的逻辑，其具有可选的缩放。执行单元包括从指定的指令源矢量寄存器中的连续位置检索数据元素并将它们存储到计算出的位置的逻辑。

9. 发明申请

WO2017117317A1 SYSTEMS, METHODS, AND APPARATUSES FOR FAULT TOLERANCE AND DETECTION 审中-公开
标题翻译：用于容错和检测的系统，方法和装置
公开(公告)号：WO2017117317A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/069062
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R.
IPC分类号： G06F11/18 , G06F15/80
CPC分类号： G06F11/079 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/3016 , G06F11/0745 , G06F11/0751 , G06F11/0772
摘要： Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.
摘要翻译：描述了用于容错和检测的系统，方法和装置。例如，一种包括复制指令的输入源的电路的设备; 算术逻辑单元（ALU）电路，用于使用单指令多数据（SIMD）硬件执行具有复制输入源的指令以产生打包数据结果; 以及耦合到ALU电路以评估打包数据结果并将奇异数据结果输出到指令的目的地的比较电路被描述。

10. 发明申请

WO2017112176A1 INSTRUCTIONS AND LOGIC FOR LOAD-INDICES-AND-PREFETCH-GATHERS OPERATIONS 审中-公开
标题翻译：指标和逻辑的负载指数和预分析运行
公开(公告)号：WO2017112176A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062708
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： YOUNT, Charles R. , VALLES, Antonio C. , GOKHALE, Indraneil M. , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F9/30029 , G06F9/30 , G06F9/3802 , G06F9/3818 , G06F15/8007
摘要： A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform a gather, and prefetch (to a specified cache) elements for a future gather from arbitrary locations in memory. The execution unit includes logic to load, for each element to be gathered or prefetched, an index value to be used in computing the address in memory for the element. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address based on the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.
摘要翻译：处理器包括执行单元以执行指令以从指数阵列加载指数，可选地执行汇集以及从存储器中的任意位置预取（到指定的高速缓存）元件以用于未来汇集。执行单元包括为每个要被收集或预取的元素加载用于计算元素在存储器中的地址的索引值的逻辑。索引值可以从为该指令识别的索引数组中检索。执行单元包括用于基于为指令指定的基地址和为数据元素检索的索引值的总和计算地址的逻辑，具有或不具有缩放。执行单元包括将收集到的数据元素存储在为指令指定的目的地向量寄存器中的连续位置中的逻辑。

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