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1. 发明申请

WO2013101227A1 VECTOR FREQUENCY COMPRESS INSTRUCTION 审中-公开
标题翻译：矢量频率压缩指令
公开(公告)号：WO2013101227A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068230
申请日：2011-12-30
申请人： INTEL CORPORATION , SAIR, Suleyman , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , DOSHI, Kshitij A. , TOLL, Bret L.
发明人： SAIR, Suleyman , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , DOSHI, Kshitij A. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/3016 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要翻译：一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。目标操作数标识目标向量寄存器。处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定的压缩值，后跟该运行的运行长度。

2. 发明申请

WO2013101223A1 EFFICIENT ZERO-BASED DECOMPRESSION 审中-公开
标题翻译：高效的基于零的分解
公开(公告)号：WO2013101223A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068226
申请日：2011-12-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译：一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。第二个掩码基于尾随零的计数。执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。将缓冲区移位并复制到结果，并将源数据元素集合向右移动。如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。

3. 发明申请

WO2013101218A1 VECTOR FREQUENCY EXPAND INSTRUCTION 审中-公开
标题翻译：矢量频率扩展指令
公开(公告)号：WO2013101218A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068217
申请日：2011-12-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R. , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30025 , G06F9/30036 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要翻译：包括硬件解码单元和执行引擎单元的处理器核心。所述硬件解码单元对矢量频率扩展指令进行解码，其中所述向量频率压缩指令包括源操作数和目的操作数，其中所述源操作数指定源向量寄存器，所述源向量寄存器包括一对或多对值和游程长度，根据运行长度将其扩展为该值的运行。执行引擎单元，用于执行解码矢量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及包括在源向量寄存器中运行长度编码的至少一个相同值的运行。

4. 发明申请

WO2013048367A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY 审中-公开
标题翻译：指导和逻辑提供矢量负载和存储条以及屏蔽功能
公开(公告)号：WO2013048367A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/053321
申请日：2011-09-26
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , DOSHI, Kshitij A. , SAIR, Suleyman , YOUNT, Charles R.
发明人： OULD-AHMED-VALL, Elmoustapha , DOSHI, Kshitij A. , SAIR, Suleyman , YOUNT, Charles R.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.
摘要翻译：指令和逻辑提供具有跨度和掩码功能的矢量加载和/或存储。一些实施例响应于指定以下内容的指令：一组加载，目的寄存器，掩码寄存器，存储器地址和步长; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的步长倍数。第一个掩码值指示该元素尚未从内存加载，第二个值指示该元素不需要或已经加载。对于具有第一值的每一个，根据掩码寄存器中的数据字段的位置生成所述步长的对应倍数，以将数据元素从存储器加载到对应的目的地寄存器位置，并且掩码寄存器中的对应值被改变到第二个值。这些说明可以在故障后重新启动。

5. 发明申请

WO2013095598A1 APPARATUS AND METHOD FOR MASK REGISTER EXPAND OPERATION 审中-公开
标题翻译：掩模注册扩展操作的装置和方法
公开(公告)号：WO2013095598A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067068
申请日：2011-12-22
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , DIXON, Martin G. , DOSHI, Kshitij A. , ABEL, James C. , LOCKTYUKHIN, Maxim , HANCOCK, Chad D. , JULIER, Michael A. , VEMURI, Navin
发明人： OULD-AHMED-VALL, Elmoustapha , DIXON, Martin G. , DOSHI, Kshitij A. , ABEL, James C. , LOCKTYUKHIN, Maxim , HANCOCK, Chad D. , JULIER, Michael A. , VEMURI, Navin
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/30109 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method are described for expanding bits from a mask register in a processor and computing system with vector registers and vector data elements. For example, a method according to one embodiment includes the following operations: reading each mask register bit stored in a mask register, the mask register containing mask values used for performing operations on vector values stored in a set of vector registers; and replicating each mask register bit N times into a destination register, where N is the number of vector elements stored in each vector register.
摘要翻译：描述了用于在处理器中的掩码寄存器扩展位的装置和方法，以及具有向量寄存器和向量数据元素的计算系统。例如，根据一个实施例的方法包括以下操作：读取存储在掩码寄存器中的每个掩码寄存器位，所述掩码寄存器包含用于对存储在一组向量寄存器中的向量值执行操作的掩码值; 并将每个掩码寄存器位N次复制到目标寄存器中，其中N是存储在每个向量寄存器中的向量元素的数量。

6. 发明申请

WO2013095592A1 APPARATUS AND METHOD FOR VECTOR COMPUTE AND ACCUMULATE 审中-公开
标题翻译：用于矢量计算和累积的装置和方法
公开(公告)号：WO2013095592A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067062
申请日：2011-12-22
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , DIXON, Martin G. , DOSHI, Kshitij A. , ABEL, James C. , LOKTYUKHIN, Maxim , HANCOCK, Chad D. , JULIER, Michael A. , VEMURI, Navin
发明人： OULD-AHMED-VALL, Elmoustapha , DIXON, Martin G. , DOSHI, Kshitij A. , ABEL, James C. , LOKTYUKHIN, Maxim , HANCOCK, Chad D. , JULIER, Michael A. , VEMURI, Navin
IPC分类号： G06F9/30 , G06F9/38 , G06F9/44
CPC分类号： G06F17/16 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： An apparatus and method are described for comparing elements between two immediate values. For example, a method according to one embodiment includes the following operations: reading values of a first set of elements stored in a first immediate value, each element having a defined element position in the first immediate value; comparing each element from the first set of elements with each of a second set of elements stored in a second immediate value; counting the number of times the value of each element of the first set of elements is found in the second set of elements to arrive at a final count for each element of the first set of elements; and transferring the final count for each element to a third immediate value, wherein the final count is stored in an element position in the third immediate value corresponding to the defined element position in the first immediate value.
摘要翻译：描述了用于比较两个立即值之间的元素的装置和方法。例如，根据一个实施例的方法包括以下操作：读取存储在第一立即值中的第一组元素的值，每个元素具有在第一立即值中的限定元素位置; 将来自第一组元素的每个元素与存储在第二立即值中的第二组元素进行比较; 对在第二组元素中找到第一组元素的每个元素的值的次数进行计数，以得到第一组元素的每个元素的最终计数; 以及将每个元素的最终计数转移到第三立即值，其中最终计数被存储在与第一立即值中定义的元素位置对应的第三立即值中的元素位置中。

7. 发明申请

WO2015094260A1 ELASTIC VIRTUAL MULTIPATH RESOURCE ACCESS USING SEQUESTERED PARTITIONS 审中-公开
标题翻译：弹性虚拟多路径资源访问使用序列分段
公开(公告)号：WO2015094260A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/076406
申请日：2013-12-19
申请人： INTEL CORPORATION , DOSHI, Kshitij A. , LE, Minh Christian , KHANNA, Rahul , DORMITZER, Paul H.
发明人： DOSHI, Kshitij A. , LE, Minh Christian , KHANNA, Rahul , DORMITZER, Paul H.
IPC分类号： G06F13/36 , G06F13/368 , G06F12/16
CPC分类号： G06F11/1471 , G06F11/2033 , G06F11/2035 , G06F11/2043 , G06F2201/805 , G06F2201/85
摘要： Technologies for virtual multipath access include a computing device configured to sequester a recovery partition from a host partition while allowing the recovery partition to access one or more resources of the host partition such as host memory or data storage. A remote computing device determines whether the host partition is responsive. The recovery partition receives a request for host state data of the host partition from the remote computing device in response to a determination that the host partition is not responsive. The recovery partition retrieves the requested host state data using a host state index maintained by the host partition and transmits the requested host state data to the remote computing device. The host state index may identify the location of the requested host state data. The remote computing device may perform a recovery operation based on the received host state data. Other embodiments are described and claimed.
摘要翻译：用于虚拟多路径访问的技术包括被配置为从主机分区隔离恢复分区的计算设备，同时允许恢复分区访问诸如主机存储器或数据存储的主机分区的一个或多个资源。远程计算设备确定主机分区是否响应。响应于确定主机分区不响应，恢复分区从远程计算设备接收对主机分区的主机状态数据的请求。恢复分区使用由主机分区维护的主机状态索引检索所请求的主机状态数据，并将所请求的主机状态数据发送到远程计算设备。主机状态索引可以标识所请求的主机状态数据的位置。远程计算设备可以基于接收到的主机状态数据执行恢复操作。描述和要求保护其他实施例。

8. 发明申请

WO2017111973A1 EFFICIENT AND SECURE SHARING OF LARGE DATA REPOSITORIES 审中-公开
标题翻译：有效和安全的大型数据存储共享
公开(公告)号：WO2017111973A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067535
申请日：2015-12-22
申请人： INTEL CORPORATION , ILLENDULA, Ajith K. , DOSHI, Kshitij A. , ZIMMER, Vincent J.
发明人： ILLENDULA, Ajith K. , DOSHI, Kshitij A. , ZIMMER, Vincent J.
IPC分类号： G06F21/60 , G06F17/30 , G06F15/16
CPC分类号： G06F15/16 , G06F17/30076 , G06F21/6227
摘要： Systems, apparatuses and methods may provide for a memory apparatus that includes a client-side address space dedicated to an accessor of obfuscated multi-tenant data, wherein an executable view generation library is stored to the client-side address space. In one example, the executable view generation library is to receive a request to access at least a portion of the obfuscated multi-tenant data, convert the obfuscated multi-tenant data to deobfuscated multi-tenant data based on metadata associated with the executable view generation library and generate a single-tenant view based on the deobfuscated multi-tenant data.
摘要翻译：系统，装置和方法可以提供一种存储装置，其包括专用于混淆的多租户数据的访问者的客户端地址空间，其中可执行的视图生成库被存储到客户端地址空间，方地址空间。在一个示例中，可执行视图生成库将接收访问经模糊化的多租户数据的至少一部分的请求，基于与可执行视图生成相关联的元数据将模糊的多租户数据转换为去混淆的多租户数据并根据反混淆的多租户数据生成单租户视图。

9. 发明申请

WO2016206110A1 METHODS AND APPARATUS TO ADAPTIVELY MANAGE DATA COLLECTION DEVICES IN DISTRIBUTED COMPUTING SYSTEMS 审中-公开
标题翻译：分布式计算系统中适应性管理数据采集设备的方法和设备
公开(公告)号：WO2016206110A1
公开(公告)日：2016-12-29
申请号：PCT/CN2015/082527
申请日：2015-06-26
申请人： INTEL CORPORATION , ZHONG, Tao , DENG, Gang , LU, Zhongyan , DOSHI, Kshitij A.
发明人： ZHONG, Tao , DENG, Gang , LU, Zhongyan , DOSHI, Kshitij A.
IPC分类号： G01R21/133
CPC分类号： H04L67/12 , H04L12/66 , H04L41/00 , H04L41/0893 , H04W4/70
摘要： Methods and apparatus to adaptively manage data collection devices in distributed computing systems are disclosed. Example disclosed methods involve instructing a first data collection device to operate according to a first rule. The example first rule specifies a first operating mode and defining a first event of interest. Example disclosed methods also involve obtaining first data from the first data collection device while operating according to the first rule. Example disclosed methods also involve, in response to determining that the first event of interest has occurred based on the first data, providing a second rule based on the first data to the first data collection device, and providing a third rule to a second data collection device. The example second rule specifies a second operating mode and defines a second event of interest, and the examples third rule specifies a third operating mode.
摘要翻译：公开了在分布式计算系统中自适应地管理数据采集设备的方法和装置。示例性公开的方法包括指示第一数据收集装置根据第一规则进行操作。示例第一规则指定第一操作模式并定义感兴趣的第一事件。公开的示例方法还涉及在根据第一规则操作的同时从第一数据收集装置获取第一数据。公开的示例方法还涉及响应于基于第一数据确定感兴趣的第一事件已经发生，基于第一数据向第一数据收集设备提供第二规则，并且向第二数据收集提供第三规则设备。示例性第二规则指定第二操作模式并定义感兴趣的第二事件，并且示例第三规则指定第三操作模式。

10. 发明申请

WO2020000335A1 SYSTEMS AND METHODS OF RESTRICTING ACCESS TO KERNEL MEMORY 审中-公开
公开(公告)号：WO2020000335A1
公开(公告)日：2020-01-02
申请号：PCT/CN2018/093526
申请日：2018-06-29
申请人： INTEL CORPORATION , SUKHOMLINOV, Vadim , DOSHI, Kshitij A. , NAYSHTUT, Alex , XI, Honghai
发明人： SUKHOMLINOV, Vadim , DOSHI, Kshitij A. , NAYSHTUT, Alex , XI, Honghai
IPC分类号： G06F12/14
摘要： Systems and methods that include kernel address detection circuitry to identify a current privilege level (CPL) of a speculatively executed instruction as either a kernel-level instruction or a user-level instruction are provided. For instructions identified as kernel-level, the kernel address detection circuitry permits access to all or a portion of both kernel memory space and user memory space within the system memory. For instructions identified as user-level, the kernel address detection circuitry permits access to all or a portion of the user memory space within the system memory. If a user-level instruction attempts to access a physical memory address within the defined kernel memory space, the kernel address detection circuitry generates an exception and does not provide the user-level instruction access to the physical address in the kernel memory space. Thus, the systems and methods prevent memory accesses used in side channel attacks such as Meltdown.

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