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1. 发明申请

WO2013162589A1 MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开
标题翻译：多核处理器的不对称计算元素之间的迁移任务
公开(公告)号：WO2013162589A1
公开(公告)日：2013-10-31
申请号：PCT/US2012/035339
申请日：2012-04-27
申请人： INTEL CORPORATION , NAVEH, Alon , YOSEF, Yuval , WEISSMANN, Eliezer , AGGARWAL, Anil , ROTEM, Efraim , MENDELSON, Avi , RONEN, Ronny , GINZBURG, Boris , MISHAELI, Michael , HAHN, Scott D. , KOUFATY, David A. , SRINIVASA, Ganapati , THERIEN, Guy
发明人： NAVEH, Alon , YOSEF, Yuval , WEISSMANN, Eliezer , AGGARWAL, Anil , ROTEM, Efraim , MENDELSON, Avi , RONEN, Ronny , GINZBURG, Boris , MISHAELI, Michael , HAHN, Scott D. , KOUFATY, David A. , SRINIVASA, Ganapati , THERIEN, Guy
IPC分类号： G06F9/46 , G06F9/22 , G06F15/80
CPC分类号： G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。描述和要求保护其他实施例。

2. 发明申请

WO2017105638A1 SYSTEMS, METHODS AND DEVICES FOR WORK PLACEMENT ON PROCESSOR CORES 审中-公开
标题翻译：用于处理器核心上的工作放置的系统，方法和设备
公开(公告)号：WO2017105638A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/059026
申请日：2016-10-27
申请人： INTEL CORPORATION
发明人： THERIEN, Guy , SOTOMAYOR, Guy , BISWAS, Arijit , POWELL, Michael D. , DEHAEMER, Eric J.
IPC分类号： G06F9/44 , G06F1/32
CPC分类号： G06F9/4856 , G06F1/3287 , G06F9/4418 , G06F9/461 , G06F9/4893 , G06F9/5094 , Y02D10/24 , Y02D10/32 , Y02D10/44
摘要： Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a CO state).
摘要翻译：
可以在处理器内核之间迁移工作。例如，可以检测到在第一个芯上造成沉重负荷的线。功率控制单元可以确定将线程从第一低效内核迁移到第二高效内核。功率控制单元可以请求第一核心和第二核心转换到低功率状态（例如，睡眠状态，C6功率状态等）。第一个核心可以将其软件上下文转移到第一个核心软件上下文存储，暂停和停顿。第二个核心可以停止和停顿。来自第一核心软件上下文存储器的软件上下文可以被传送到第二核心的第二核心软件上下文存储器。第一核的处理核标识符可以被分配给第二核。然后功率控制单元可以请求第二个内核转换到活动状态（例如CO状态）。

3. 发明申请

WO2022132276A1 HARDWARE AND SOFTWARE COORDINATED COST-AWARE LOW POWER STATE SELECTION 审中-公开
公开(公告)号：WO2022132276A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/052075
申请日：2021-09-24
申请人： INTEL CORPORATION
发明人： KIRUBAKARAN, Deepak S , SIVAKUMAR, Ramakrishnan , FENGER, Russell , GUPTA, Monica , DAI, Jianwei , SAKARDA, Premanand , THERIEN, Guy , CHABUKSWAR, Rajshree , GUTIERREZ, Chad , THOMAS, Renji
IPC分类号： G06F1/329 , G06F1/3293 , G06F9/48 , G06F9/50
摘要： A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

4. 发明申请

WO2017086914A1 EXTENDED VISUAL CAPTURE IN A RECONFIGURABLE DEVICE 审中-公开
标题翻译：可重构设备中的可扩展视觉捕获
公开(公告)号：WO2017086914A1
公开(公告)日：2017-05-26
申请号：PCT/US2015/060844
申请日：2015-11-16
申请人： INTEL CORPORATION
发明人： SARRAJU, Rajiva K. , ZUNIGA, Joshua L. , MAGI, Aleksander , BROWNING, David W. , YOUNKIN, Audrey C. , KAMPPARI, Saara , RIEHL, Phil , THERIEN, Guy
IPC分类号： H04N5/225 , H04N5/232
CPC分类号： H04N5/2258 , G06F1/1626 , G06F1/1652 , G06F1/1677 , G06F1/1686 , H04N5/2257 , H04N5/23245 , H04N5/23293 , H04N5/23296 , H04N5/247
摘要： The present disclosure pertains to extended visual capture in a reconfigurable device. In general, at least a display portion of a device may have a deformable shape configuration in that its shape is changeable by a user. The device may also comprise at least sensor circuitry including a plurality of sensors. The shape configuration may position the plurality of sensors at different positions to enable extended visual capture of a 180 to 360 degree viewing range surrounding the device in a single image or video. Control circuitry in the device may determine when shape reconfiguration of at least the display has occurred, determine whether the new shape configuration involves visual capture, and if the new shape configuration is determined to involve visual capture, determine an operational mode for the at least the sensor circuitry and cause the sensor circuitry to capture visual data based at least on the operational mode.
摘要翻译：本公开涉及可重构设备中的扩展视觉捕捉。通常，装置的至少显示部分可具有可变形的形状配置，因为其形状可由用户改变。该设备还可以至少包括包括多个传感器的传感器电路。形状配置可以将多个传感器定位在不同的位置处，以在单个图像或视频中实现对设备周围180°至360°观看范围的扩展视觉捕捉。设备中的控制电路可以确定何时至少显示器的形状重新配置已经发生，确定新形状配置是否涉及视觉捕捉，并且如果确定新形状配置涉及视觉捕捉，则确定用于至少传感器电路并且使得传感器电路至少基于操作模式来捕获视觉数据。

5. 发明申请

WO2004031924A3 LIMIT INTERFACE FOR PERFORMANCE MANAGEMENT 审中-公开
公开(公告)号：WO2004031924A3
公开(公告)日：2004-04-15
申请号：PCT/US2003/029501
申请日：2003-09-19
申请人： INTEL CORPORATION
发明人： THERIEN, Guy
IPC分类号： G06F1/20
摘要： In one embodiment of the invention, an environmental condition relating to a first device is monitored. The first device operates in a first performance state. A limit command is generated based on the environmental condition requesting the first device to adjust the first performance state to a second performance state.

6. 发明公开

EP3109731A1 MAPPING A PERFORMANCE REQUEST TO AN OPERATING FREQUENCY IN A PROCESSOR 有权
标题翻译：艾滋病艾滋病毒感染者艾滋病艾滋病艾滋病
公开(公告)号：EP3109731A1
公开(公告)日：2016-12-28
申请号：EP16176907.0
申请日：2014-06-24
申请人： Intel Corporation
发明人： ROTEM, Efraim , ROSENZWEIG, Nir , WEISSMANN, Eliezer , DIEFENBAUGH, Paul , THERIEN, Guy
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/152
摘要： In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括各自独立地执行指令的多个核心和耦合到多个核心的功率控制单元（PCU），以控制处理器的功耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能量表值，并且至少部分地基于性能量表值来计算动态性能频率映射。描述和要求保护其他实施例。

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